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features ? high-performance, low-power atmel ? avr ? xmega ? 8/16-bit microcontroller ? nonvolatile program and data memories ? 64k - 128kbytes of in-system self-programmable flash ? 4k - 8kbytes boot section ? 2kbytes eeprom ? 4k - 8kbytes internal sram ? peripheral features ? two-channel dma controller ? four-channel event system ? two 16-bit timer/counters one timer/counter with 4 output compare or input capture channels one timer/counter with 2 output compare or input capture channels high resolution extensions one timer/counter advanced waveform extension (awex) on timer/counter split mode on timer/counter ? one usb device interface usb 2.0 full speed (12mbps) and low speed (1.5mbps) device compliant 32 endpoints with full configuration flexibility ? one usart with irda support ? aes and des crypto engine ? crc-16 (crc-ccitt) and crc-32 (ieee 802.3) generator ? one two-wire interface with dual address match (i 2 c and smbus compatible) ? one serial peripheral interface (spi) ? 16-bit real time counter (rtc) with separate oscillator ? liquid crystal display 4x25 segment driver built in contrast control ascii character mappinggra flexible swap of segment and common terminals buses ? one eight-channel, 12-bit, 300 thousand sps analog to digital converter ? two analog comparators with window compare function, and current source feature ? external interrupts on all general purpose i/o pins ? programmable watchdog timer with separate on-chip ultra low power oscillator ? qtouch ? library support capacitive touch buttons, sliders and wheels ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal and external clock options with pll ? programmable multilevel interrupt controller ? five sleep modes ? programming and debug interfaces jtag (ieee 1149.1 compliant) interface, including boundary scan pdi (program and debug interface) ? i/o and packages ? 36 programmable i/o pins ? 64 - lead tqfp ? 64 - pad qfn ? operating voltage ? 1.6 ? 3.6v ? operating frequency ? 0 ? 12mhz from 1.6v ? 0 ? 32mhz from 2.7v 8/16-bit atmel xmega b3 microcontroller atxmega128b3 atxmega64b3 8074b?avr?02/12
2 8074b?avr?02/12 xmega b3 typical applications 1. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation. 2. pb-free packaging, complies to the european directive for restriction of hazardous substances (rohs directive). also halide f ree and fully green. 3. for packaging information, see ?errata? on page 130 ? industrial control ? climate control ? low power battery applications ? factory automation ? rf and zigbee ? power tools ? building control ? usb connectivity ? hvac ? board control ? sensor control ? utility metering ? white goods ? optical ? medical applications ordering code flash (bytes) eeprom (bytes) sram (bytes) speed (mhz) power supply package (1)(2)(3) temp atxmega128b3-au 128k + 8k 2k 8k 32 1.6 - 3.6v 64a -40 c - 85 c atxmega64b3-au 64k + 4k 2k 4k ATXMEGA128B3-MH 128k + 8k 2k 8k 64m2 atxmega64b3-mh 64k + 4k 2k 4k package type 64a 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.5mm lead pitch, thin profile plastic quad flat package (tqfp) 64m2 64-pad, 9x9x1.0mm body, lead pitch 0.05mm, 7.65mm exposed pad, quad flat no-lead package (qfn)
3 8074b?avr?02/12 xmega b3 2. pinout/block diagram figure 2-1. block diagram and pinout note: 1. for full details on pinout and alternate pin functions refer to ?pinout and pin functions? on page 56 . pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 2 3 4 5 6 7 8 1 9 vcc gnd 10 pd0 pd1 12 11 pdi / reset pdi 13 14 vcc gnd 15 16 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 41 40 39 38 37 36 35 34 33 bias2 bias1 vlcd capl caph 48 47 46 45 44 vcc gnd 43 42 54 53 pr0 pr1 64 pb0 pb1 pb2 pb3 pb6 pb7 pb4 pb5 63 62 60 60 59 58 57 52 51 50 49 com3 com2 com0 com1 56 avcc agnd 55 25 26 27 28 29 30 31 32 pm0 / seg16 pm1 / seg15 pm2 / seg14 pm3 / seg13 pm4 / seg12 pm5 / seg11 pm6 / seg10 pm7 / seg9 17 18 19 20 21 22 23 24 pg0 / seg24 pg1 / seg23 pg2 / seg22 pg3 / seg21 pg4 / seg20 pg5 / seg19 pg6 / seg18 pg7 / seg17 power supervision event routing network dma controller bus controller sram flash ocd prog/dbg interface eeprom event sys. controller watchdog timer watchdog oscillator osc/clk control real time counter interrupt controller data bus data bus sleep controller reset controller tempref vref port r crypto / crc cpu port b adc ac0:1 aref jtag port d port c tc0:1 usart0 twi spi ircom usb sram lcd pwr com seg port m port g seg lcd controller digital function analog function / oscillators programming, debug, test external clock / crystal pins general purpose i/o ground lcd power
4 8074b?avr?02/12 xmega b3 3. overview the atmel ? avr ? xmega ? b3 microcontroller is a family of low-power, high-performance, and peripheral-rich cmos 8/16-bit microcontrollers based on the avr enhanced risc architecture. by executing instructions in a single clock cycle, the atmel avr xm ega b3 device achieves throughputs cpu approach ing one million instructions per seco nd (mips) per me gahertz, allow- ing the system designer to optimize power consumption versus processing speed. the avr cpu combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent reg- isters to be accessed in a single instruction, executed in one clock cycle. the resulting architecture is more code efficient while achi eving throughputs many times faster than conven- tional single-accumula tor or cisc based microcontrollers. the atmel avr xmega b3 devices provide the following features: in-system programmable flash with read-while-write capabilities; intern al eeprom and sram ; two-channel dma controller, four-channel event system and programmable multilevel interrupt controller, 36 general purpose i/o lines, real-time counter (r tc); liquid crystal display (lcd) supporting 4x25 segment driver, ascii character mapping and built-in contrast control (lcd); two flexible, 16-bit timer/counters with compare and pwm channels; one usart; one two-wire serial interface (twi); one full speed usb 2.0 interface; one serial peripheral interface (spi); aes and des cryptographic engine; one 8-channel 12-bit adcs with programmable gain; two analog comparators (acs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators wit h pll and prescaler; and programmable brown-out detection. the program and debug interface (pdi), a fast, two-pin interface for programming and debug- ging, is available. the devices al so have an ieee std. 1149.1 co mpliant jtag inte rface, and this can also be used for on-chip debug and programming. the xmega b3 devices have five software se lectable power saving modes. the idle mode stops the cpu while allowing the sram, dma controller, event system, interrupt controller, and all peripherals to continue functioning. the power-down mode saves the sram and register contents, but stops the oscillators , disabling all other functions un til the next twi, usb resume, or pin-change interrupt, or reset. in power-save mode, the asynchronous real-time counter con- tinues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in power-save mode, the lcd controller is allowed to refresh data to the panel. in standby mode, the external crysta l oscillator keeps running while th e rest of the device is sleep- ing. this allows very fast startup from the external crystal, combined with low power consumption. in extended standby mode, both the main oscillator and the asynchronous timer continue to run, and the lcd controller is allowed to refresh data to the panel. to further reduce power consumption, the peripheral clock to eac h individual peripheral can optionally be stopped in active mode and idle sleep mode. atmel offers a free qtouch ? library for embedding capacitive touch buttons, sliders and wheels functionality into avr microcontrollers. the devices are manufactured using atmel hi gh-density, nonvolatile memory technology. the program flash memory can be reprogrammed in-system through the pdi or jtag interfaces. a boot loader running in the device can use any interface to download the application program to the flash memory. the boot loader software in t he boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining
5 8074b?avr?02/12 xmega b3 an 8/16-bit risc cpu with in-system, self-programmable flash, the atmel xmega b3 is a pow- erful microcontroller family that provides a hi ghly flexible and cost effective solution for many embedded applications. the atmel avr xmega b3 devices are supported with a full suite of program and system devel- opment tools, including c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
6 8074b?avr?02/12 xmega b3 3.1 block diagram figure 3-1. xmega b3 block diagram power supervision por/bod & reset port b (8) event routing network dma controller bus matrix sram adcb acb ocd port m (8) pdi seg[16..9] / pm[0..7] seg[0..8] com[0..3] pb[0..7] / jtag watchdog timer watchdog oscillator interrupt controller data bus prog/debug controller vcc gnd port r (2) pr[0..1] oscillator control real time counter event system controller jtag pdi_data reset / pdi_clk port b sleep controller des crc ircom port g (8) seg[24..17] / pg[0..7] lcd power[0..4] aes int. refs. arefb tempref vcc/10 cpu nvm controller flash eeprom data bus xtal2 / tosc2 xtal1 / tosc1 oscillator circuits/ clock generation pd[0..1] port d (2) usb port c (8) pc[0..7] tcc0:1 usartc0 twic spic event routing network lcd digital function analog function / oscillators programming, debug, test external clock / crystal pins general purpose i/o ground lcd power
7 8074b?avr?02/12 xmega b3 4. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 4.1 recommended reading ?xmega ? b manual ? xmega application notes this device data sheet only contains part specific information with a short description of each peripheral and module. the xmega b manual describes the modules and peripherals in depth. the xmega application notes contain example code and show applied use of the modules and peripherals. all documentations are available from www.atmel.com/avr . 5. capacitive touch sensing the atmel ? qtouch ? library provides a simple to use solution to realize touch sensitive inter- faces on most atmel avr ? microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and incl udes fully debounced reporting of touch keys and includes adja- cent key suppression ? (aks?) technology for unambiguous detection of key events. the qtouch library includes support for the qtouch and qmatrix acquisition methods. touch sensing can be added to any application by linking the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch chan- nels and sensors, and then calling the touch sens ing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from the atmel website.
8 8074b?avr?02/12 xmega b3 6. avr cpu 6.1 features ? 8/16-bit, high-performan ce atmel avr risc cpu ? 142 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in ram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16mb of program memory and 16mb of data memory ? true 16/24-bit access to 16/24-bit i/o registers ? efficient support for 8-, 16-, and 32-bit arithmetic ? configuration change protectio n of system-critical features 6.2 overview the atmel ? avr ? xmega ? devices use the 8/16-bit avr cpu. the main function of the cpu is to execute the code and perform all calculations. the cpu is able to access memories, perform calculations, control peripherals, and execute t he program in the flash memory. interrupt han- dling is described in a separate section, refer to ?interrupts and programmable multilevel interrupt controller? on page 29 . 6.3 architectural overview in order to maximize performance and parallelis m, the avr cpu uses a harvard architecture with separate memories and buses for program and data. instructions in the program memory are executed with single-level pipelining. wh ile one instruction is being executed, the next instruction is pre-fetched from the program memory. this enables instructions to be executed on every clock cycle. for details of all avr instructions, refer to http://www.atmel.com/avr. figure 6-1. block diagram of the avr cpu architecture.
9 8074b?avr?02/12 xmega b3 the arithmetic logic unit (alu) supports arit hmetic and logic operations between registers or between a constant and a register. single-register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. the alu is directly connected to the fast-acces s register file. the 32 x 8-bit general purpose working registers all have single clock cycle acce ss time allowing single-cycle arithmetic logic unit (alu) operation between registers or between a register and an immediate. six of the 32 registers can be used as three 16-bit address po inters for program and data space addressing, enabling efficient address calculations. the memory spaces are linear. the data memory space and the program memory space are two different memory spaces. the data memory space is divided into i/o registers and sram. in addition, the eeprom can be memory mapped in the data memory. all i/o status and control registers reside in the lowest 4kb addresses of the data memory. this is referred to as the i/o memory space. the lowe st 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3f. the re st is the extended i/o memory space, ranging from 0x0040 to 0x0fff. i/o registers here must be accessed as data space locations using load (ld/lds/ldd) and store (s t/sts/std) instructions. the sram holds data. code execution from sram is not supported. it can easily be accessed through the five different addressing modes s upported in the avr architecture. the first sram address is 0x2000. data addresses 0x1000 to 0x1fff are reserved for memory mapping of eeprom. the program memory is divided in two sections, the application program section and the boot program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that is used for self-programmi ng of the application flash memory must reside in the boot program section. the application section contains an application table section with sep- arate lock bits for write and read/write protection. the application table section can be used for save storing of nonvolatile data in the program memory. 6.4 alu - arithmetic logic unit the arithmetic logic unit (alu) supports arit hmetic and logic operations between registers or between a constant and a register. single-register operations can also be executed. the alu operates in direct connection with all 32 general purpose registers. in a single clock cycle, arith- metic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. alu operations are divided into three main categories ? arithmetic, logical, and bit functions. both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementa- tion of 32-bit aritmetic. the hardware multiplier supports signed and unsigned multiplication and fractional format.
10 8074b?avr?02/12 xmega b3 6.4.1 hardware multiplier the multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. the hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: ?multiplication of unsigned integers ?multiplication of signed integers ?multiplication of a signed integer with an unsigned integer ?multiplication of unsigned fractional numbers ?multiplication of signed fractional numbers ?multiplication of a signed fractional number with an unsigned one a multiplication takes two cpu clock cycles. 6.5 program flow after reset, the cpu starts to execute instructions from the lowest address in the flash program- memory ?0.? the program counter (pc) addresses the next instruction to be fetched. program flow is provided by conditional and unco nditional jump and call instructions capable of addressing the whole address space directly. most avr instructions use a 16-bit word format, while a limited number use a 32-bit format. during interrupts and subroutine calls, the return address pc is stored on the stack. the stack is allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. after reset, the stack pointer (sp) points to the highest address in the internal sram. the sp is read/write accessible in the i/o memory space, enabling easy implementation of multiple stacks or stack areas. the data sram can easily be accessed through the five different addressing modes supported in the avr cpu. 6.6 status register the status register (sreg) cont ains information about the result of the most recently executed arithmetic or logic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the stat us register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. this must be handled by software. the status register is accessible in the i/o memory space. 6.7 stack and stack pointer the stack is used for storing return addresses after interrupts and subroutine calls. it can also be used for storing temporary data. the stack pointer (sp) register always points to the top of the stack. it is implemented as two 8-bit registers t hat are accessible in the i/o memory space. data are pushed and popped from the stack using the push and pop instructions. the stack grows from a higher memory location to a lower memory location. this implies that pushing data onto the stack decreases the sp, and popping data off the stack increases the sp. the sp is auto- matically loaded after reset, and the initial value is the highest address of the internal sram. if the sp is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
11 8074b?avr?02/12 xmega b3 during interrupts or subroutine calls, the return address is automatically pushed on the stack. the return address can be two or three bytes, depending on program memory size of the device. for devices with 128kb or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. for devices with more than 128kb of pro- gram memory, the return address is three bytes, and hence the sp is decremented/incremented by three. the return address is popped off the stack when returning from interrupts using the reti instruction, and from subroutine calls using the ret instruction. the sp is decremented by one when data are pushed on the stack with the push instruction, and incremented by one when data is popped off the stack using the pop instruction. to prevent corruption when updating the stack pointer from software, a write to spl will auto- matically disable interrupts for up to four instructions or until the next i/o memory write. 6.8 register file the register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. the register file supports the following input/output schemes: ?one 8-bit output operand and one 8-bit result input ?two 8-bit output operands and one 8-bit result input ?two 8-bit output operands and one 16-bit result input ?one 16-bit output operand and one 16-bit result input six of the 32 registers can be used as three 16 -bit address register pointers for data space addressing, enabling efficient address calculati ons. one of these address pointers can also be used as an address pointer for look up tables in flash program memory.
12 8074b?avr?02/12 xmega b3 7. memories 7.1 features ? flash program memory ? one linear address space ? in-system programmable ? self-programming and boot loader support ? application section for applic ation code ? application table section for application code or data storage ? boot section for applicatio n code or bootloader code ? separate read/write protectio n lock bits for all sections ? built in fast crc check of a selectable flash program memory section ? data memory ? one linear address space ? single-cycle access from cpu ? sram ? eeprom byte and page accessible optional memory mapping for direct load and store ? i/o memory configuration and status register s for all peripherals and modules 4 bit-accessible general purpose regist ers for global variables or flags ? bus arbitration safe and deterministic handlin g of priority between cpu, dma controller, and other bus masters ? separate buses for sram, eeprom and i/o memory simultaneous bus access for cpu and dma controller ? production signature row memory for factory programmed data ? id for each microcontroller device type ? serial number for each device ? calibration bytes for factory calibrated peripherals ? user signature row ? one flash page in size ? can be read and written from software ? content is kept after chip erase 7.2 overview the atmel avr architecture has two main memory spaces, the program memory and the data memory. executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. the data memory includes the internal sram, and eeprom for nonvolatile data storage. all memory spaces are linear and require no memory bank switching. nonvolatile me mory (nvm) spaces can be locked for further write and read/write operations. this prevents unrestricted access to the application software. a separate memory section contains the fuse bytes. these are used for configuring important system functions, and can only be written by an external programmer. the available memory size configurations are shown in ?ordering information? on page 2 . in addition, each device has a flash memory signature row for calibration data, device identifica- tion, serial number etc.
13 8074b?avr?02/12 xmega b3 7.3 flash program memory the atmel ? avr ? xmega ? devices contain on-chip, in-system reprogrammable flash memory for program storage. the flash memory can be accessed for read and write from an external pro- grammer through the pdi or from application software running in the device. all avr cpu instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. the flash memory is organized in two main sections, the application section and the boot loader sec- tion. the sizes of the different sections are fixed, but device-dependent. these two sections have separate lock bits, and can have different levels of protection. the store program memory (spm) instruction, which is used to write to the flash from the a pplication software, will only oper- ate when executed from the boot loader section. the application section contains an application table section with separate lock settings. this enables safe storage of nonvolatile data in the program memory. 7.3.1 application section the application section is the section of the flash that is used for storing the executable applica- tion code. the protection level for the application section can be selected by the boot lock bits for this section. the application section ca n not store any boot loader code since the spm instruction cannot be executed from the application section. 7.3.2 application table section the application table section is a part of the application section of the flash memory that can be used for storing data. the size is identical to the boot loader section. the protection level for the application table section can be selected by the boot lock bits for this section. the possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. if this section is not used for data, application code can reside here. 7.3.3 boot loader section while the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the spm instruction can only initiate pro- gramming when executing from this section. t he spm instruction can access the entire flash, including the boot loader section itself. the protection level for the boot loader section can be selected by the boot loader lock bits. if this se ction is not used for boot loader software, applica- tion code can be stored here. figure 7-1. flash program memory (hexadecimal address) word address 0 application section (128k/64k) ... efff / 77ff f000 / 7800 application table section (8k/4k) ffff / 7fff 10000 / 8000 boot section (8k/4k) 10fff / 87ff
14 8074b?avr?02/12 xmega b3 7.3.4 production signature row the production signature row is a separate memory section for factory programmed data. it con- tains calibration data for functions such as oscillators and analog modules. some of the calibration values will be automa tically loaded to th e corresponding module or peripheral unit during reset. other values must be loaded from the signature row and written to the correspond- ing peripheral registers from software. for details on calibration conditions, refer to ?electrical characteristics? on page 68 . the production signature row also contains an id that identifies each microcontroller device type and a serial number for each manufactured device. the serial number consists of the production lot number, wafer number, and wafer coordinates fo r the device. the device id for the available devices is shown in table 7-1 on page 14 . the production signature row cannot be written or erased, but it can be read from application software and external programmers. table 7-1. device id bytes for xmega b3 devices. 7.3.5 user signature row the user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. it is one flash page in size, and is meant for static user parameter storage, such as cali bration data, custom serial number, identification numbers, random number seeds, etc. this section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. this ensures parameter storage dur- ing multiple program/erase operations and on-chip debug sessions. 7.4 fuses and lock bits the fuses are used to configure important system functions, and can only be written from an external programmer. the application software can read the fuses. the fuses are used to config- ure reset sources such as brownout detector and watchdog, startup configuration, jtag enable, and jtag user id. the lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be blocked). lock bits can be written by external programmers and applica- tion software, but only to stricter protection levels. chip erase is the only way to erase the lock bits. to ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. an unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. both fuses and lock bits are reprogrammable like the flash program memory. 7.5 data memory the data memory contains the i/o memory, internal sram and optionally memory mapped eeprom. the data memory is organized as one continuous memory section, see figure 7-2 on page 15 . to simplify development, i/o memory, eeprom and sram will always have the same start addresses for all xmega devices. device device id bytes byte 2 byte 1 byte 0 atxmega64b3 51 96 1e atxmega128b3 4b 97 1e
15 8074b?avr?02/12 xmega b3 7.6 eeprom xmega b3 devices have eeprom for nonvolatile data storage. it is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. the eeprom supports both byte and page access. memory mapped eeprom allows highly effi- cient eeprom reading and eeprom buffer loadi ng. when doing this, eeprom is accessible using load and store instructions. memory m apped eeprom will always start at hexadecimal address 0x1000. 7.7 i/o memory the status and configuration registers for peripherals and modules, including the cpu, are addressable through i/o memory locations. all i/o locations can be accessed by the load (ld/lds/ldd) and store (st/sts/std) instructions, which are used to transfer data between the 32 registers in the register file and the i/o memory. the in and out instructions can address i/o memory locations in the range of 0x00 to 0x3f directly. in the address range 0x00 - 0x1f, single-cycle instructions fo r manipulation and checking of individual bits are available. the i/o memory address for all peripherals and modules in xmega b3 is shown in the ?periph- eral module address map? on page 61 . 7.7.1 general purpose i/o registers the lowest 4 i/o memory addresses are reserved as general purpose i/o registers. these regis- ters can be used for storing global variables and flags, as they are directly bit-accessible using the sbi, cbi, sbis, an d sbic instructions. 7.8 data memory and bus arbitration since the data memory is organized as four separate sets of memories, the different bus mas- ters (cpu, dma controller read and dma controller write, etc.) can access different memory sections at the same time. 7.9 memory timing read and write access to the i/o memory takes one cpu clock cycle. a write to sram takes one cycle, and a read from sram takes two cycles . for burst read (dma), new data are avail- able every cycle. eeprom page lo ad (write) takes one cycle, and three cycles are required for read. for burst read, new data are available every second cycle. refer to the instruction sum- mary for more details on instructions and instruction timing. figure 7-2. data memory map (hexadecimal address) byte address atxmega128b3 byte address atxmega64b3 0 i/o registers (4k) 0 i/o registers (4k) fff fff 1000 eeprom (2k) 1000 eeprom (2k) 17ff 17ff reserved reserved 2000 internal sram (8k) 2000 internal sram (4k) 3fff 2fff
16 8074b?avr?02/12 xmega b3 7.10 device id and revision each device has a three-byte device id. this id identifies atmel as the manufacturer of the device and the device type. a separate register contains the revision number of the device. 7.11 jtag disable it is possible to disable the jtag interface from the applicatio n software. this will prevent all external jtag access to the device until the next device reset or until jtag is enabled again from the application software. as long as jtag is disabled, the i/o pins required for jtag can be used as normal i/o pins. 7.12 i/o memory protection some features in the device are regarded as critical for safety in some applications. due to this, it is possible to lock the i/o register related to the clock system, the event system, and the advanced waveform extensions. as long as the lock is enabled, all related i/o registers are locked and they can not be written from the application software. the lock registers themselves are protected by the configuration change protection mechanism. 7.13 flash and eeprom page size the flash program memory and eeprom data memory are organi zed in pages. the pages are word accessible for the flash an d byte accessible for the eeprom. table 7-2 on page 16 shows the flash program memory organization. flash write and erase operations are performed on one page at a time, while reading the flash is done one byte at a time. for flash access the z-pointer (z[m:n]) is used for addressing. the most significant bits in the address (fpage) give the page number and the least significant address bits (fword) give the word in the page. table 7-2. number of words and pages in the flash. table 7-3 on page 16 shows eeprom memory organiza tion for the xmega b3 devices. eeeprom write and erase operatio ns can be perfo rmed one page or one by te at a time, while reading the eeprom is don e one byte at a time. for eeprom access the nvm address regis- ter (addr[m:n]) is used for addre ssing. the most significant bits in the address (e2page) give the page number and the least significant address bits (e2byte) give the byte in the page. table 7-3. number of bytes and pages in the eeprom. devices pc size flash size page size fword fpage application boot (bits) (bytes) (words) size no of pages size no of pages atxmega64b3 16 64k + 4k 128 z[7:1] z[16:8] 64k 256 4k 16 atxmega128b3 17 128k + 8k 128 z[7:1] z[17:8] 128k 512 8k 32 devices eeprom page size e2byte e2page no of pages size (bytes) atxmega64b3 2k 32 addr[4:0] addr[10:5] 64 atxmega128b3 2k 32 addr[4:0] addr[10:5] 64
17 8074b?avr?02/12 xmega b3 8. dmac ? direct memory access controller 8.1 features ? allows high speed data transfer s with minimal cpu intervention ? from data memory to data memory ? from data memory to peripheral ? from peripheral to data memory ? from peripheral to peripheral ? two dma channels with separate ? transfer triggers ? interrupt vectors ? addressing modes ? programmable channel priority ? from 1 byte to 16mb of data in a single transaction ? up to 64kb block transfers with repeat ? 1, 2, 4, or 8 byte burst transfers ? multiple addressing modes ? static ?incremental ? decremental ? optional reload of source and dest ination addresses at the end of each ?burst ?block ? transaction ? optional interrupt on end of transaction ? optional connection to crc ge nerator for crc on dma data 8.2 overview the two-channel direct memory access (dma) controller can transfer data between memories and peripherals, and thus offload these tasks from the cpu. it enables high data transfer rates with minimum cpu intervention, and frees up cpu time. the four dma channels enable up to four independent and parallel transfers. the dma controller can move data between sram and peripherals, between sram locations and directly between peripheral registers. with access to all peripherals, the dma controller can handle automatic transfer of data to/from communication modules. the dma controller can also read from memo ry mapped eeprom. data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. they build block transfers of configurable size from 1 byte to 64kb. a repeat counter can be used to repeat each block trans- fer for single transactions up to 16mb. sour ce and destination addressing can be static, incremental or decremental. automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. application software, peripherals, and events can trigger dma transfers. the two dma channels have individual configuration and control settings. this include source, destination, transfer triggers, and transaction size s. they have individual interrupt settings. inter- rupt requests can be generated when a transacti on is complete or when the dma controller detects an error on a dma channel. to allow for continuous transfers, the channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa.
18 8074b?avr?02/12 xmega b3 9. event system 9.1 features ? system for direct peripheral-to-peripheral communication and signaling ? peripherals can directly send, receiv e, and react to peripheral events ? cpu and dma controller independent operation ? 100% predictable signal timing ? short and guaranteed response time ? four event channels for up to four different and parallel signal routings and configurations ? events can be sent and/or used by most peripherals, clock system, and software ? additional func tions include ? quadrature decoders ? digital filtering of i/o pin state ? works in active mode and idle sleep mode 9.2 overview the event system enables direct peripheral-to-peripheral communication and signaling. it allows a change in one peripheral?s state to automatically trigger actions in other peripherals. it is designed to provide a predictable system for short and predictable response times between peripherals. it allows for autonomous peripheral control and interaction without the use of inter- rupts, cpu, or dma controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. it also allows for synchronized timing of actions in several peripheral modules. a change in a peripheral?s state is referred to as an event, and usually corresponds to the peripheral?s interrupt conditions. events can be directly passed to other peripherals using a ded- icated routing network called the event routing network. how events are routed and used by the peripherals is configured in software. figure 9-1 on page 19 shows a basic diagram of all connected peripherals. the event system can directly connect together analog and digital converters, analog comparators, i/o port pins, the real-time counter, timer/counters, ir communication module (ircom), and usb interface. it can also be used to trigger dma transactions (dma controller). events can also be generated from software and the peripheral clock.
19 8074b?avr?02/12 xmega b3 figure 9-1. event system overview and connected peripherals. the event routing network consis ts of four software-configurable multiplexers that control how events are routed and used. these are called event channels, and allow for up to four parallel event configurations and routings. the maximum routing latency is two peripheral clock cycles. the event system works in both active mode and idle sleep mode. timer / counters usb real time counter port pins cpu / software dma controller ircom adc event system controller clk per prescaler ac event routing network
20 8074b?avr?02/12 xmega b3 10. system clock and clock options 10.1 features ? fast start-up time ? safe run-time clock switching ? internal oscillators: ? 32mhz run-time calibrated oscillator ? 2mhz run-time calib rated oscillator ? 32.768khz calibrated oscillator ? 32khz ultra low power (ulp) oscillator with 1khz output ? external clock options ? 0.4mhz - 16mhz cr ystal oscillator ? 32.768khz crystal oscillator ? external clock ? pll with 20mhz - 128mhz output frequency ? internal and external clock opti ons and 1x to 31x multiplication ? lock detector ? clock prescalers with 1x to 2048x division ? fast peripheral clocks running at 2 and 4 times the cpu clock ? automatic run-time calibration of internal oscillators ? external oscillator and pll lock failure dete ction with optional non-maskable interrupt 10.2 overview atmel avr xmega b3 devices have a flexible clo ck system supporting a large number of clock sources. it incorporat es both accurate internal oscillators and external crystal oscillator and res- onator support. a high-frequency phase locked lo op (pll) and clock prescalers can be used to generate a wide range of clock frequencies. a calibration feature (dfll) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. an oscillator failur e monitor can be enabled to issue a non-maskable interrupt and switch to the in ternal oscillator if the exte rnal oscillator or pll fails. when a reset occurs , all clock sources except the 32khz ul tra low power oscilla tor are disabled. after reset, the device will alwa ys start up running from the 2mhz internal oscillator. during nor- mal operation, the system clock source and pres calers can be changed from software at any time. figure 10-1 on page 21 presents the principal clock system in the xmega b family of divices. not all of the clocks need to be active at a gi ven time. the clocks for the cpu and peripherals can be stopped using sleep modes and power reduction registers, as described in ?power man- agement and sleep modes? on page 24 .
21 8074b?avr?02/12 xmega b3 figure 10-1. the clock system, clock sources and clock distribution. 10.3 clock sources the clock sources are divided in two main grou ps: internal oscillators and external clock sources. most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. after reset, the device starts up running from the 2mhz internal oscillator. the other clock sources, dflls and pll, are turned off by default. the internal osc illators do not require any external components to run. for details on character- istics and accuracy of the internal osc illators, refer to the device datasheet. real time counter peripherals ram avr cpu non-volatile memory watchdog timer brown-out detector system clock prescalers usb prescaler system clock multiplexer (sclksel) pllsrc div32 32 khz int. ulp 32.768 khz int. osc 32.768 khz tosc 2mhz int. osc 32 mhz int. osc 0.4 ? 16 mhz xtal div32 div32 div4 pll usbsrc to s c 1 tosc2 x tal1 xtal2 clk sys clk rtc clk per2 clk per clk cpu clk per4 clk usb lcd clk lcd p c[7:0] xoscsel rtcsrc
22 8074b?avr?02/12 xmega b3 10.3.1 32khz ultra low power internal oscillator this oscillator provides an approximate 32khz cl ock. the 32khz ultra low power (ulp) internal oscillator is a very low power cl ock source, and it is not design ed for high accuracy.the oscillator employs a built-in prescaler th at provides a 1khz output. the oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. this oscillator can be selected as the clock source for the rtc and for lcd. 10.3.2 32.768khz calibrated internal oscillator this oscillator provides an appr oximate 32.768khz clock. it is calibrated during production to provide a default frequency close to its nominal frequency. the calibration register can also be written from software for run-time calibration of the o scillator frequency. t he oscillator employs a built-in prescaler, which provid es both a 32.768kh z output and a 1.024khz output. this oscilla- tor can be used as a clock source for the sy stem clock, rtc and lcd, and as the dfll reference clock. 10.3.3 32.768khz crystal oscillator a 32.768khz crystal oscillator can be connec ted between the tosc1 and tosc2 pins and enables a dedicated low fr equency oscillator input circuit. a low power mode with reduced volt- age swing on tosc2 is available. this oscillator can be used as a clock source for the system clock, rtc and lcd, and as the dfll reference clock. 10.3.4 0.4 - 16mhz crystal oscillator this oscillator can operate in four different modes optimized fo r different freque ncy ranges, all within 0.4mhz - 16mhz. 10.3.5 2mhz run-time calibrated internal oscillator the 2mhz run-time calibrated inte rnal oscillator is the default sy stem clock source after reset. it is calibrated during production to provide a default frequency close to its nominal frequency. a dfll can be enabled fo r automatic run-time ca libration of the oscillato r to compensate for tem- perature and vo ltage drift and optimize the oscillator accuracy. 10.3.6 32mhz run-time calibrated internal oscillator the 32mhz run-time calibra ted internal oscillator is a high-re quency oscillator. it is calibrated during production to provide a default frequency close to its nominal frequency. a digital fre- quency looked loop (dfl l) can be enabled for au tomatic run-time calibra tion of the oscillator to compensate for temperature and voltage drift and optim ize the oscillator accuracy. this oscilla- tor can also be adjusted and calibrated to any frequency between 30mhz and 55mhz. the production signature row contai ns 48mhz calibration values in tended used when the oscillator is used a full-speed usb clock source. 10.3.7 external clock sources the xtal1 and xtal2 pins can be us ed to drive an external oscilla tor, either a quartz crystal or a ceramic resonator. xtal1 or each pin of port c can be used as input for an external clock sig- nal. the tosc1 and tosc2 pins are dedicated to driving a 32.768khz crystal oscillator.
23 8074b?avr?02/12 xmega b3 10.3.8 pll with 1x-31x multiplication factor the built-in phase locked loop (pll) can be used to generate a high-frequency system clock. the pll has a user-selectable multiplication factor of from 1 to 31. in combination with the pres- calers, this gives a wide range of output frequencies from all clock sources.
24 8074b?avr?02/12 xmega b3 11. power management and sleep modes 11.1 features ? power management for adjusting power consumption and functions ? five sleep modes ?idle ?power down ? power save ?standby ? extended standby ? power reduction register to disable clock and tu rn off unused peripherals in active and idle modes 11.2 overview various sleep modes and clock gating are provided in order to tailor power consumption to appli- cation requirements. this enables the xmega microcontroller to stop unused modules to save power. all sleep modes are available and can be entered from active mode. in active mode, the cpu is executing application code. when the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. the applicat ion code decides which sleep mode to enter and when. interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. in addition, power reduction registers provide a method to stop the clock to individual peripherals from software. when this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. this reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 11.3 sleep modes sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. xmega microcontrollers have five different sleep modes tuned to match the typ- ical functional stages during application execution. a dedicated sleep instruction (sleep) is available to enter sleep mode. interrupts are us ed to wake the device from sleep, and the avail- able interrupt wake-up sources are dependent on the configured sleep mode. when an enabled interrupt occurs, the device will wake up and exec ute the interrupt service routine before con- tinuing normal program execution from the first inst ruction after the sleep instruction. if other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. after wake-up, the cpu is halted for four cycles before execution starts. the content of the register file, sram and registers are kept during sleep. if a reset occurs dur- ing sleep, the device will reset, start up, and execute from the reset vector. 11.3.1 idle mode in idle mode the cpu and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and dma controller are kept runnin g. any enabled interrupt will wake the device.
25 8074b?avr?02/12 xmega b3 11.3.2 power-down mode in power-down mode, all clocks, including the real-time counter clock source, are stopped. this allows operation only of asynchronous modules that do not require a running clock. the only interrupts that can wake up the mcu are the two-wire interface address match interrupt, asyn- chronous port interrupts, and the usb resume interrupt. 11.3.3 power-save mode power-save mode is identical to power down, with two exceptions: 1. if the real-time counter (rtc) is enabled, it will keep running during sleep, and the device can also wake up from either an rtc overflow or compare match interrupt. 2. if the liquid crystal display controller (lcd) is enabled, it will keep running during sleep, and the device can wake up from lcd frame completed interrupt. 11.3.4 standby mode standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the cpu, per ipheral, rtc and lcd clocks are stopped. this reduces the wake-up time. 11.3.5 extended standby mode extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the cpu and peripheral clocks are stopped. this reduces the wake-up time.
26 8074b?avr?02/12 xmega b3 12. system control and reset 12.1 features ? reset the microcontroller and set it to in itial state when a re set source goes active ? multiple reset sources that cover different situations ?power-on reset ? external reset ? watchdog reset ? brownout reset ? pdi reset ? software reset ? asynchronous operation ? no running system clock in the device is required for reset ? reset status register for reading the reset source from the application code 12.2 overview the reset system issues a microcontroller reset and sets the device to its initial state. this is for situations where operation should not start or c ontinue, such as when the microcontroller oper- ates below its power supply rating. if a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. the i/o pins are immediately tri-stated. the program counter is set to the reset vector location, and all i/o registers are set to their initial values. the sram content is kept. however, if the device accesses the sram when a reset occurs, the content of the accessed location can not be guaranteed. after reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. by default, this is the lowest pro- gram memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. the reset functionality is asynchronous, and so no running system clock is required to reset the device. the software reset feature makes it possible to issue a controlled system reset from the user software. the reset status register has individual status flags for each reset source. it is cleared at power- on reset, and shows which sources have issued a reset since the last power-on. 12.3 reset sequence a reset request from any reset so urce will immediately reset the device and keep it in reset as long as the request is active. when all reset r equests are released, t he device will go through three stages before the device starts running again: ?reset counter delay ?oscillator startup ?oscillator calibration if another reset requests occurs during this pr ocess, the reset sequence will start over again.
27 8074b?avr?02/12 xmega b3 12.4 reset sources 12.4.1 power-on reset a power-on reset (por) is generated by an on-chi p detection circuit. the por is activated when the v cc rises and reaches the por threshold voltage (v pot ), and this will start the reset sequence. the por is also activated to power down the device properly when the v cc falls and drops below the v pot level. the v pot level is higher for falling v cc than for rising v cc . consult the datasheet for por charac- teristics data. 12.4.2 brownout detection the on-chip brownout detection (bod) circuit monitors the v cc level during operation by com- paring it to a fixed, programmable level t hat is selected by the bodl evel fuses. if disabled, bod is forced on at the lowest level during chip erase and when the pdi is enabled. 12.4.3 external reset the external reset circuit is connected to th e external reset pin. the external reset will trigger when the reset pin is driven below the reset pin threshold voltage, v rst , for longer than the minimum pulse period, t ext . the reset will be held as long as the pin is kept low. the reset pin includes an internal pull-up resistor. 12.4.4 watchdog reset the watchdog timer (wdt) is a system function for monitoring correct program operation. if the wdt is not reset from the software within a programmable timout period, a watchdog reset will be given. the watchdog re set is active for one to two clock cycl es of the 2mhz internal oscillator. for more details see ?wdt ? watchdog timer? on page 28 . 12.4.5 software reset the software reset makes it possible to issue a sy stem reset from software by writing to the soft- ware reset bit in the reset control register.t he reset will be issued within two cpu clock cycles after writing the bit. it is not possible to execute any instruction from when a software reset is requested until it is issued. 12.4.6 program and debug interface reset the program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debuggin g. this reset source is accessible only from external debuggers and programmers.
28 8074b?avr?02/12 xmega b3 13. wdt ? watchdog timer 13.1 features ? issues a device reset if the timer is not reset before its timeout period ? asynchronous operation fr om dedicated oscillator ? 1khz output of the 32khz ultra low power oscillator ? 11 selectable timeout periods, from 8ms to 8s ? two operation modes: ? normal mode ? window mode ? configuration lock to prevent unwanted changes 13.2 overview the watchdog timer (wdt) is a system function for monitoring correct program operation. it makes it possible to recover from error situat ions such as runaway or deadlocked code. the wdt is a timer, configured to a predefined timeout period, and is constantly running when enabled. if the wdt is not reset within the timeout period, it will issue a microcontroller reset. the wdt is reset by executing the wdr (watchdog timer reset) instruction from the application code. the window mode makes it possible to define a time slot or window inside the total timeout period during which wdt must be reset. if the wd t is reset outside this window, either too early or too late, a system reset will be issued. compared to the normal mode, this can also catch sit- uations where a code error causes constant wdr execution. the wdt will run in active mode and all sleep modes, if enabled. it is asynchronous, runs from a cpu-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. the configuration change protection mechanism ensures that the wdt settings cannot be changed by accident. for increased safety, a fuse for locking the wdt settings is also available.
29 8074b?avr?02/12 xmega b3 14. interrupts and programmable mu ltilevel interrupt controller 14.1 features ? short and predictable interrupt response time ? separate interrupt configuration and vector address for each interrupt ? programmable multilevel interrupt controller ? interrupt prioritizing according to level and vector address ? three selectable interrupt levels for all interrupts: low, medium and high ? selectable, round-robin priority scheme within low-level interrupts ? non-maskable interrupts for critical functions ? interrupt vectors optionally pl aced in the application section or the boot loader section 14.2 overview interrupts signal a change of state in peripherals, and this can be used to alter program execu- tion. peripherals can have one or more interrupts, and all are individually enabled and configured. when an inte rrupt is enabled and co nfigured, it will generat e an interr upt request when the interrupt condition is present. the pr ogrammable multilevel inte rrupt controller (pmic) controls the handling and prioritizing of interrup t requests. when an interrupt request is acknowl- edged by the pmic, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. all peripherals can select between three different priority levels for their interrupts: low, medium, and high. interrupts are prioritized according to their level and their interrupt vector address. medium-level interrupts will interrupt low-level in terrupt handlers. high-level interrupts will inter- rupt both medium- and low-level interrupt handlers. within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. non-maskable interrupts (nmi) are also supported, and can be used for system critical functions. 14.3 interrupt vectors the interrupt vector is the sum of the peripheral?s base interrupt address and the offset address for specific interrupts in each peripheral. the base addresses for the xmega b3 devices are shown in table 14-1 . offset addresses for each interrupt available in the peripheral are described for each peripheral in the xmega b manual. for peripherals or modules that have only one interrupt, the interrupt vector is shown in table 14-1 . the program address is the word address. table 14-1. reset and interrupt vectors program address (base address) source interrupt description 0x000 reset 0x002 oscf_int_vect crystal oscillato r failure interrupt vector (nmi) 0x004 portc_int_base port c interrupt base 0x008 portr_int_base port r interrupt base 0x00c dma_int_base dma controller interrupt base
30 8074b?avr?02/12 xmega b3 0x014 rtc_int_base real time counter interrupt base 0x018 twic_int_base two-wire interface on port c interrupt base 0x01c tcc0_int_base timer/counter 0 on port c interrupt base 0x028 tcc1_int_base timer/counter 1 on port c interrupt base 0x030 spic_int_vect spi on port c interrupt vector 0x032 usartc0_int_base usart 0 on port c interrupt base 0x03e usb_int_base usb on port d interrupt base 0x046 lcd_int_base lcd interrupt base 0x048 aes_int_vect aes interrupt vector 0x04a nvm_int_base non-volatile memory interrupt base 0x04e portb_int_base port b interrupt base 0x052 acb_int_base analog comparator on port b interrupt base 0x058 adcb_int_base analog to digital converter on port b interrupt base 0x060 portd_int_base port d interrupt base 0x064 portg_int_base port g interrupt base 0x068 portm_int_base port m interrupt base table 14-1. reset and interrupt vectors (continued) program address (base address) source interrupt description
31 8074b?avr?02/12 xmega b3 15. i/o ports 15.1 features ? 36 general purpose input and output pins with individual configuration ? output driver with configurable driver and pull settings: ? totem-pole ? wired-and ?wired-or ? bus-keeper ? inverted i/o ? input with synchronous and/or asynchronous sensing with interrupts and events ? sense both edges ? sense rising edges ? sense falling edges ? sense low level ? optional pull-up and pull-down resistor on input and wired-or/and configurations ? optional slew rate control ? asynchronous pin change sensing that can wake the device from all sleep modes ? two port interrupts with pin masking per i/o port ? efficient and safe access to port pins ? hardware read-modify-write through dedicated togg le/clear/set registers ? configuration of multiple pins in a single operation ? mapping of port registers in to bit-accessible i/o memory space ? peripheral clocks output on port pin ? real-time counter cloc k output to port pin ? event channels can be output on port pin ? remapping of digital peripheral pin functions ? selectable usart, spi, and timer/ counter input/output pin locations 15.2 overview one port consists of up to eight port pins: pin 0 to 7. each port pin can be configured as input or output with configurable driver and pull settings . they also implement synchronous and asyn- chronous input sensing with interrupts and events for selectable pin change conditions. asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. all functions are individual and configurable per pin, but several pins can be configured in a sin- gle operation. the pins have hardware read- modify-write (rmw) functionality for safe and correct change of drive value and/or pull resistor configuration. the direction of one port pin can be changed without unintentionally changing the direction of any other pin. the port pin configuration also controls input and output selection of other device functions. it is possible to have both the peripheral clock and the real-time clock output to a port pin, and avail- able for external use. the same applies to events from the event system that can be used to synchronize and control external functions. other digital peripherals, such as usart, spi, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. the notation of the ports are portb, portc, portd, portg, portm and portr.
32 8074b?avr?02/12 xmega b3 15.3 output driver all port pins (pn) have programmable output configuration. the port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 push-pull figure 15-1. i/o configuration - totem-pole 15.3.2 pull-down figure 15-2. i/o configuration - totem-pole with pull-down (on input) 15.3.3 pull-up figure 15-3. i/o configuration - totem-pole with pull-up (on input) inn outn dirn pn inn outn dirn pn inn outn dirn pn
33 8074b?avr?02/12 xmega b3 15.3.4 bus-keeper the bus-keeper?s weak output produces the same logi cal level as the last output level. it acts as a pull-up if the last leve l was ?1?, and pull-down if the last level was ?0?. figure 15-4. i/o configuration - totem-pole with bus-keeper 15.3.5 others figure 15-5. output configuration - wired-or with optional pull-down figure 15-6. i/o configuration - wired-and with optional pull-up inn outn dirn pn inn outn pn inn outn pn
34 8074b?avr?02/12 xmega b3 15.4 input sensing input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in figure 15-7 on page 34 . figure 15-7. input sensing system overview when a pin is configured with inverted i/o, the pin value is inverted before the input sensing. 15.5 alternate port functions most port pins have alternate pin functions in addition to being a general purpose i/o pin. when an alternate function is enabled, it might override the normal port pin function or pin value. this happens when other peripherals that require pins are enabled or configured to use pins. if and how a peripheral will override and use pins is described in the section for that peripheral. ?pinout and pin functions? on page 56 shows which modules on peripherals that enable alternate func- tions on a pin, and which alternate functions that are available on a pin. inverted i/o interrupt control ireq event pn d q r d q r synchronizer inn edge detect asynchronous sensing synchronous sensing edge detect
35 8074b?avr?02/12 xmega b3 16. t/c ? 16-bit timer/counter type 0 and 1 16.1 features ? two 16-bit ti mer/counters ? one timer/counter of type 0 ? one timer/counter of type 1 ? 32-bit timer/counter support by cascading two timer/counters ? up to four compare or capture (cc) channels ? four cc channels for ti mer/counters of type 0 ? two cc channels for timer/counters of type 1 ? double buffered timer period setting ? double buffered capture or compare channels ? waveform generation: ? frequency generation ? single-slope pulse width modulation ? dual-slope pulse width modulation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture ? timer overflow and er ror interrupts/events ? one compare match or input capture interrupt/event per cc channel ? can be used with event system for: ? quadrature decoding ? count and direction control ?capture ? can be used with dma and to trigger dma transactions ? high-resolution extension ? increases frequency and waveform reso lution by 4x (2-bi t) or 8x (3-bit) ? advanced waveform extension: ? low- and high-side output with pr ogrammable dead-time insertion (dti) ? event controlled fault protection for safe disabling of drivers 16.2 overview atmel avr xmega b3 devices have a set of tw o flexible 16-bit timer/counters (tc). their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. a timer/counter consists of a base counter and a set of compare or capture (cc) channels. the base counter can be used to count clock cycles or events. it has direction control and period set- ting that can be used for timing. the cc channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. a timer/counter can be configured for either capture or com- pare functions, but cannot perform both at the same time.
36 8074b?avr?02/12 xmega b3 a timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. the event system can also be used for direction control and capture trig- ger or to synchronize operations. there are two differences between timer/counter type 0 and type 1. timer/counter 0 has four cc channels, and timer/counter 1 has two cc channe ls. all information related to cc channels 3 and 4 is valid only for timer/counter 0. only timer/counter 0 has the split mode feature that split it into 2 8-bit timer/counters with four compare channels each. some timer/counters have extensions to enable more specialized waveform and frequency gen- eration. the advanced waveform extension (awex) is intended for motor control and other power control applications. it enables low- and high-side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. it can also generate a syn- chronized bit pattern across the port pins. the advanced waveform extension can be enabl ed to provide extra and more advanced fea- tures for the timer/counter. this are onl y available for timer/counter 0. see ?tc2 ?16-bit timer/counter type 2? on page 37 for more details. the high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clo ck source running up to four times faster than the peripheral clock. see ?hi-res ? high resolution extension? on page 39 for more details. figure 16-1. overview of a timer/counter and closely related peripherals portc has one timer/counter 0 and one timer/counter1. notation of these are tcc0 (time/counter c0), a nd tcc1 respectively. awex compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator hi-res fault protection capture control base counter counter control logic timer period prescaler dead-time insertion pattern generation clk per4 port event system clk per timer/counter
37 8074b?avr?02/12 xmega b3 17. tc2 ?16-bit timer/counter type 2 17.1 features ? a system of two eigh t-bit timer/counters ? low-byte timer/counter ? high-byte timer/counter ? eight compare channels ? four compare channels for the low-byte timer/counter ? four compare channels for the high-byte timer/counter ? waveform generation ? single slope pulse width modulation ? timer underflow interrupts/events ? one compare match interrupt/event per compar e channel for the low-byte timer/counter ? can be used with the even t system for count control ? can be used to trigger dma transactions ? high-resolution extension in creases frequency and wavefo rm resolution by 4x or 8x 17.2 overview a timer/counter 2 is realized when a timer/counter 0 is set in split mode. it is a system of two eight-bit timer/counters, each with four compare channels. this results in eight configurable pulse width modulation (pwm) chan nels with individually controlle d duty cycles, and is intended for applications that require a high number of pwm channels. the two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. the differ ence between them is that only the low-byte timer/counter can be used to generate compare match interrupts, events and dma triggers. the two eight-bit timer/counters have a shared clock source and separate period and compare settings. they can be clocked and timed from the peripheral clock, with optional prescaling, or from the event system. the counters are always counting down. the timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one timer/counter can exist only as either type 0 or type 2. portc has one timer/counter 2. its notation is tcc2 (time/counter c2).
38 8074b?avr?02/12 xmega b3 18. awex ? advanced waveform extension 18.1 features ? waveform output with complementar y output from each compare channel ? four dead-time inser tion (dti) units ? 8-bit resolution ? separate high and low side dead-time setting ? double buffered dead time ? optionally halts timer during dead-time insertion ? pattern generation unit creating synchronised bit pattern across the port pins ? double buffered pattern generation ? optional distribution of one compare channel output across the port pins ? event controlled fault protection for in stant and predictable fault triggering 18.2 overview the advanced waveform extension (awex) provides extra functions to the timer/counter in waveform generation (wg) modes. it is primarily intended for use with different types of motor control and other power control applications. it ena bles low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. it can also gener- ate a synchronized bit pattern across the port pins. each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any awex features are enabled. these output pairs go through a dead- time insertion (dti) unit that generates the non-inverted low side (ls) and inverted high side (hs) of the wg output with dead-time insertion between ls and hs switching. the dti output will override the normal port value acco rding to the port override setting. the pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. in addition, the wg output from compare channel a can be distributed to and override all the port pins. when the pattern generat or unit is enabled, the dti unit is bypassed. the fault protection unit is conn ected to the event system, enablin g any event to trigger a fault condition that will disabl e the awex output. the event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. the awex is available for tcc0. the notation of this is awexc.
39 8074b?avr?02/12 xmega b3 19. hi-res ? high r esolution extension 19.1 features ? increases waveform generator resolution up to 8x (3 bits) ? supports frequency, single-slope pwm, and dual-slope pwm generation ? supports the awex when this is used for the same timer/counter 19.2 overview the high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. it can be used for a timer/counter doing frequency, single-slope pwm, or dual-slope pw m generation. it can also be used with the awex if this is used for the same timer/counter. the hi-res extension uses the peripheral 4x clock (clk per4 ). the system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than the peripheral and cpu clock frequency when the hi-res extension is enabled. atmel avr xmega b3 devices have one hi-r es extension that can be enabled for the timer/counters pair on portc. th e notation of this is hiresc.
40 8074b?avr?02/12 xmega b3 20. rtc ? 16-bit real-time counter 20.1 features ? 16-bit resolution ? selectable clock source ? 32.768khz external crystal ? external clock ? 32.768khz internal oscillator ? 32khz internal ulp oscillator ? programmable 10-bit clock prescaling ? one compare register ? one period register ? clear counter on period overflow ? optional interrupt/event on overflow and compare match 20.2 overview the 16-bit real-time counter (rtc) is a counter that typically runs continuously, including in low- power sleep modes, to keep track of time. it ca n wake up the device from sleep modes and/or interrupt the device at regular intervals. the reference clock is typically the 1.024khz output from a high-accuracy crystal of 32.768khz, and this is the configuration most optimized for low power consumption. the faster 32.768khz output can be selected if the rtc needs a resolution higher than 1ms. the rtc can also be clocked from an external clock signal, the 32.768khz internal oscillator or the 32khz internal ulp oscillator. the rtc includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. a wide range of resolutions and time-out periods can be config- ured. with a 32.768khz clock source, the maximu m resolution is 30.5s, and time-out periods can range up to 2000 seconds. with a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). the rtc can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. figure 20-1. real-time counter overview 32.768khz crystal osc 32.768khz int. osc tosc1 tosc2 external clock div32 div32 32khz int ulp (div32) rtcsrc 10-bit prescaler clk rtc cnt per comp = = ?match?/ compare top/ overflow
41 8074b?avr?02/12 xmega b3 21. usb ? universal serial bus interface 21.1 features ? one usb 2.0 full speed (12m bps) and low speed (1.5mbps) device compliant interface ? integrated on-chip usb transceiver , no external components needed ? 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints ? one input endpoint per endpoint address ? one output endpoint per endpoint address ? endpoint address transfer type selectable to ? control transfers ? interrupt transfers ? bulk transfers ? isochronous transfers ? configurable data payload size per endpoint, up to 1023 bytes ? endpoint configuration and data buffers located in internal sram ? configurable location for endpoint configuration data ? configurable location for each endpoint's data buffer ? built-in direct memory access (dma) to internal sram for: ? endpoint configurations ? reading and writing endpoint data ? ping-pong operation for higher throughput and double buffered operation ? input and output endpoint data buffers used in a single direction ? cpu/dma controller can update data buffer during transfer ? multipacket transfer for reduced inte rrupt load and software intervention ? data payload exceeding maximum packet size is transferred in on e continuous transfer ? no interrupts or software interact ion on packet transaction level ? transaction complete fifo for workflow ma nagement when using multiple endpoints ? tracks all completed transactions in a first-come, first-served work queue ? clock selection independent of sys tem clock source and selection ? minimum 1.5mhz cpu clock requir ed for low speed usb operation ? minimum 12mhz cpu clock required for full speed operation ? connection to event system ? on chip debug possibilities during usb transactions 21.2 overview the usb module is a usb 2.0 full speed (12m bps) and low speed (1.5mbps) device compliant interface. the usb supports 16 endpoint addresses. all endpoint addresses have one input and one out- put endpoint, for a total of 31 configurable endpoints and one control endpoint. each endpoint address is fully configurable and can be configured for any of the four transfer types: control, interrupt, bulk, or isochronous. the data payload size is also selectable, and it supports data payloads up to 1023 bytes. no dedicated memory is allocate d for or included in the usb mo dule. internal sram is used to keep the configuration for each endpoint address and the data buffer for each endpoint. the memory locations used for endpoint configurations and data buffers are fully configurable. the amount of memory allocated is fully dynamic, according to the number of endpoints in use and
42 8074b?avr?02/12 xmega b3 the configuration of these. the usb module has built-in direct memory access (dma), and will read/write data from/to the sram when a usb transaction takes place. to maximize throughput, an endpoint address can be configured for ping-pong operation. when done, the input and output endpoints are both used in the same direction. the cpu or dma con- troller can then read/write one data buffer while the usb module writes/reads the others, and vice versa. this gives double buffered communication. multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. this reduces the cpu inter- vention and the interrupts needed for usb transfers. for low-power operation, the usb module can put the microcontroller into any sleep mode when the usb bus is idle and a suspend condition is given. upon bus resumes, the usb module can wake up the microcontroller from any sleep mode. portd has one usb. notation of this is usb.
43 8074b?avr?02/12 xmega b3 22. twi ? two wire interface 22.1 features ? one two-wire interface peripheral ? bidirectional, two-wire communication interface ? phillips i 2 c compatible ? system management bus (smbus) compatible ? bus master and slave operation supported ? slave operation ? single bus master operation ? bus master in multi-master bus environment ? multi-master arbitration ? flexible slave address match functions ? 7-bit and general call address recognition in hardware ? 10-bit addressing supported ? address mask register for dual a ddress match or address range masking ? optional software address recognitio n for unlimited number of addresses ? slave can operate in all sleep modes, including power-down ? slave address match can wake device from all sleep modes ? 100khz and 400khz bus frequency support ? slew-rate limited output drivers ? input filter for bus noise and spike suppression ? support arbitration between start/repeated start and data bit (smbus) ? slave arbitration allows support for ad dress resolve protocol (arp) (smbus) 22.2 overview the two-wire interface (twi) is a bidirectional , two-wire communication interface. it is i 2 c and system management bus (smbus) compatible. the only external hardware needed to imple- ment the bus is one pull-up resistor on each bus line. a device connected to the bus must act as a master or a slave. the master initiates a data trans- action by addressing a slave on the bus and telling whet her it wants to trans mit or receive data. one bus can have many slaves and one or several masters that can take control of the bus. an arbitration process handles priority if more than one master tries to transmit data at the same time. mechanisms for resolving bus contention are inherent in the protocol. the twi module supports master and slave functionality. the master and slave functionality are separated from each other, and can be enabled and configured separately. the master module supports multi-master bus operation and arbitration. it contains the baud rate generator. both 100khz and 400khz bus frequency is supported. quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. the slave module implements 7-bit address match and general address call recognition in hard- ware. 10-bit addressing is also supported. a dedicated address mask register can act as a second address match register or as a register for address range masking. the slave continues to operate in all sleep modes, including power-down mode. this enables the slave to wake up the device from all sleep modes on twi address match. it is possible to disable the address matching to let this be handled in software instead. the twi module will detect start and stop condi tions, bus collisions, and bus errors. arbitra- tion lost, errors, collision, and cl ock hold on the bus ar e also detected and indicated in separate status flags available in both master and slave modes.
44 8074b?avr?02/12 xmega b3 it is possible to disable the twi drivers in the device, and enable a four-wire digital interface for connecting to an external twi bus driver. this can be used for applications where the device operates from a different v cc voltage than used by the twi bus. portc has one twi. notation of this peripheral is twic.
45 8074b?avr?02/12 xmega b3 23. spi ? serial peripheral interface 23.1 features ? one spi peripheral ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? eight programmable bit rates ? interrupt flag at th e end of transmission ? write collision flag to indicate data collision ? wake up from idle sleep mode ? double speed master mode 23.2 overview the serial peripheral interfac e (spi) is a high-speed synchronous data transfer interface using three or four pins. it allows fast communication between an xmega device and peripheral devices or between several microcontrollers. the spi supports full-duplex communication. a device connected to the bus must act as a master or slave.the master initiates and controls all data transactions. portc has one spi. notation of this peripheral is spic.
46 8074b?avr?02/12 xmega b3 24. usart 24.1 features ? one usart peripheral ? full-duplex operation ? asynchronous or synchronous operation ? synchronous clock rates up to 1/ 2 of the device clock frequency ? asynchronous clock rates up to 1/8 of the device clock frequency ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? fractional baud rate generator ? can generate desired baud rate from any system clock frequency ? no need for external oscill ator with certain frequencies ? built-in error detection and correction schemes ? odd or even parity generation and parity check ? data overrun and framing error detection ? noise filtering includes false start bit detection and digital low-pass filter ? separate interrupts for ? transmit complete ? transmit data register empty ? receive complete ? multiprocessor co mmunication mode ? addressing scheme to address a specific devices on a multidevice bus ? enable unaddressed devices to automatically ignore all frames ? master spi mode ? double buffered operation ? configurable data order ? operation up to 1/2 of th e peripheral clock frequency ? ircom module for irda compliant pulse modulation/demodulation 24.2 overview the universal synchronous and asynchronous seri al receiver and transmitter (usart) is a fast and flexible serial communication module. the usart supports full-duplex communication and asynchronous and synchronous operation. the usart can be configured to operate in spi master mode and used for spi communication. communication is frame based, and the frame format can be customized to support a wide range of standards. the usart is buffered in both directions, enabling continued data transmis- sion without any delay between frames. separat e interrupts for receive and transmit complete enable fully interrupt driven communication. frame error and buffer overflow are detected in hardware and indicated with separate status flags. even or odd parity generation and parity check can also be enabled. the clock generator includes a fractional baud rate generator that is able to generate a wide range of usart baud rates from any system cloc k frequencies. this removes the need to use an external crystal oscillator wit h a specific frequency to achiev e a required baud rate. it also supports external clock input in synchronous slave operation. when the usart is set in master spi mode, all usart-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. pin control and interrupt generation are identical in both modes. the registers are used in both modes, but their functionality differs for some control settings. an ircom module can be enabled for one usart to support irda 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. portc has one usart. notation of this peripheral is usartc0.
47 8074b?avr?02/12 xmega b3 25. ircom ? ir communication module 25.1 features ? pulse modulation/demodulation for infrared communication ? irda compatible for baud rates up to 115.2kbps ? selectable pulse modulation scheme ? 3/16 of the baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built-in filtering ? can be connected to and used by any usart 25.2 overview xmega devices contain an infrared communication module (ircom) that is irda compatible for baud rates up to 115.2kbps. it can be connected to any usart to enable infrared pulse encod- ing/decoding for that usart.
48 8074b?avr?02/12 xmega b3 26. aes and des crypto engine 26.1 features ? data encryption standard (des) cpu instruction ? advanced encryption stan dard (aes) crypto module ? des instruction ? encryption and decryption ? des supported ? encryption/decryption in 16 cpu clock cycles per 8-byte block ? aes crypto module ? encryption and decryption ? supports 128-bit keys ? supports xor data load mode to the state memory ? encryption/decryption in 375 clock cycles per 16-byte block 26.2 overview the advanced encrypti on standard (aes) and da ta encryption standar d (des) are two com- monly used standards for cryptography. these are sup ported through an aes peripheral module and a des cpu instruction, and the communication interfaces and the cpu can use these for fast, encrypted communication and secure data storage. des is supported by an instruction in the avr cp u. the 8-byte key and 8-byte data blocks must be loaded into the register file, and then the des instruction must be executed 16 times to encrypt/decrypt the data block. the aes crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. the key and data must be loaded into the key and state memory in the module before encryp- tion/decryption is started. it takes 375 peripheral clock cycles before the encryption/decryption is done. the encrypted/encrypted data can then be read out, and an optional interrupt can be gen- erated. the aes crypto module also has dma support with trans fer triggers when encryption/decryption is done and optional auto- start of encryption/decryption when the state memory is fully loaded.
49 8074b?avr?02/12 xmega b3 27. crc ? cyclic redundancy check generator 27.1 features ? cyclic redundancy check (crc) generation and checking for ? communication data ? program or data in flash memory ? data in sram and i/o memory space ? integrated with flash memo ry, dma controller and cpu ? continuous crc on data going through a dma channel ? automatic crc of the complete or a selectable range of the flash memory ? cpu can load data to the crc ge nerator through the i/o interface ? crc polynomial software selectable to ? crc-16 (crc-ccitt) ? crc-32 (ieee 802.3) ? zero remainder detection 27.2 overview a cyclic redundancy check (crc) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data trans- mission, and data present in the data and program memories. a crc takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. when the same data are later received or read, the device or application repeats the calculation. if the new crc result does not match the one calculated earlier, the block contains a data error. the application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. typically, an n-bit crc applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2 -n of all longer error bursts. the crc module in xmega devices sup- ports two commonly used crc polynomials; crc-16 (crc-ccitt) and crc-32 (ieee 802.3). ? crc-16: ? crc-32: polynomial: x 16 + x 12 + x 5 +1 hex value: 0x1021 polynomial: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 hex value: 0x04c11db7
50 8074b?avr?02/12 xmega b3 28. lcd - liquid cryst al display controller 28.1 features ? display capacity up to 25 segments and up to 4 common terminals ? supports up to 16 gpio's ? shadow display memory gives fu ll freedom in segment update ? ascii character mapping ? swap capability option on segment and/or common terminal buses ? supports from static up to 1/4 duty ? supports static and 1/3 bias ? lcd driver active in power save mode for low power operation ? software selectable low power waveform ? flexible selection of frame frequency ? programmable blink mode and frequency on two segment terminals ? uses only 32 khz rtc clock source ? on-chip lcd power supply ? software contrast adjustment control ? equal source and sink capabilit y to increase glass life time ? extended interrupt mode for display update or wake-up from sleep mode 28.2 overview the lcd controller is intended for monochrome passive liquid crystal display (lcd) with up to 4 common terminals and up to 25 segments terminals. if the application does not need all the lcd segments available on the xmega, up to 16 of the unused lcd pins can be used as gen- eral purpose i/o pins. the lcd controller can be clocked by an inter nal or an external asynchronous 32khz clock source. this 32khz oscillator sour ce selection is the same as fo r the real time counter (rtc). dedicated low power waveform, contrast control, extended interrupt mode, selectable frame frequency and blink functionality are supported to offload the cpu, reduce interrupts and reduce power consumption. to reduce hardware design complexity, the lcd includes integrated lcd buffers, an integrated power supply voltage and an innovative swap mode. using swap mode, the hardware design- ers have more flexibility during board layout as they can rearrange the pin sequence on segment and/or common terminal buses. figure 28-1. lcd overview com[3:0] vlcd bias1 bias2 analog switch array shadow display memory control & swap timing character mapping caph capl seg[24:0] display memory lcd power supply
51 8074b?avr?02/12 xmega b3 29. adc ? 12-bit analog to digital converter 29.1 features ? one analog to digital converter (adc) ? 12-bit resolution ? up to 300 thousand samples per second ? down to 2.3s conversion time with 8-bit resolution ? down to 3.35s conversion time with 12-bit resolution ? differential and si ngle-ended input ? up to 16 single-ended inputs ? 16x4 differential inputs without gain ? 16x4 differential input with gain ? built-in differential gain stage ? 1/2 x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options ? single, continuous and scan conversion options ? three internal inputs ? internal temperature sensor ?v cc voltage divided by 10 ? 1.1v bandgap voltage ? internal and external reference options ? compare function for accurate monito ring of user defined thresholds ? optional event triggered co nversion for accurate timing ? optional dma transfer of conversion results ? optional interrupt/even t on compare result 29.2 overview the adc converts analog signals to digital values . the adc has 12-bit resolution and is capable of converting up to 300 thousan d samples per second (ksps). t he input selection is flexible, and both single-ended and differential measurements can be done. for differential measure- ments, an optional gain stage is available to increase the dynamic range. in addition, several internal signal inputs are available. the adc can provide both signed and unsigned results. the adc measurements can either be started by application software or an incoming event from another peripheral in the device. the adc measur ements can be started with predictable timing, and without software intervention. it is possibl e to use dma to move adc results directly to memory or peripherals when conversions are done. both internal and external reference voltages can be used. an integrated temperature sensor is available for use with the adc. the output from the v cc /10 and the bandgap voltage can also be measured by the adc. the adc has a compare function for accurate monitoring of user defined thresholds with mini- mum software intervention required.
52 8074b?avr?02/12 xmega b3 figure 29-1. adc overview the adc may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop- agation delay) from 3.35s for 12-bit to 2.3s for 8-bit result. adc conversion results are provided left- or right adjusted with optional ?1? or ?0? padding. this eases calculation when the result is represented as a signed integer (signed 16-bit number). portb has one adc. notation of this peripheral is adcb. ch0 result compare register < > threshold (int req) internal 1.00v internal vcc/1.6v arefa arefb v inp v inn internal signals internal vcc/2 adc0 adc15 ? ? ? adc0 adc7 ? ? ? reference voltage adc
53 8074b?avr?02/12 xmega b3 30. ac ? analog comparator 30.1 features ? two analog comparators (ac) ? selectable hysteresis ?no ?small ?large ? analog comparator output available on pin ? flexible input selection ? all pins on the port ? bandgap reference voltage ? a 64-level programmable voltage scaler of the internal v cc voltage ? interrupt and event generation on: ? rising edge ? falling edge ?toggle ? window function interrupt and event generation on: ? signal above window ? signal inside window ? signal below window ? constant current source with configurable output pin selection 30.2 overview the analog comparator (ac) compares the voltage levels on two inputs and gives a digital out- put based on this comparison. the analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. one important property of the analog comparator?s dynamic behavior is the hysteresis. this parameter may be adjusted in order to achieve the optimal operation for each application. the input selection includes analog port pins, several internal signals, and a 64-level program- mable voltage scaler. the analog comparator output state can also be output on a pin for use by external devices. a constant current source can be enabled and output on a selectable pin. this can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. the analog comparators are always grouped in pairs on each port. these are called analog comparator 0 (ac0) and analog comparator 1 (ac1). they have identical behavior, but separate control registers. used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. portb has one ac pair. notation is acb.
54 8074b?avr?02/12 xmega b3 figure 30-1. analog comparator overview the window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in figure 30-2 .. figure 30-2. analog comparator window function + ac0 - voltage scaler acnmuxctrl + ac1 - acnctrl interrupt mode enable enable hysteresis hysteresis bandgap ac1out winctrl interrupt sensititivity control & window function events interrupts ac0out pin input pin input pin input pin input ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events
55 8074b?avr?02/12 xmega b3 31. programming and debugging 31.1 features ? programming ? external programming through pdi or jtag interfaces minimal protocol overhead for fast operation built-in error detection and handling for reliable operation ? boot loader support for programming through any comm unication interface ? debugging ? nonintrusive, real-ti me, on-chip debug system ? no software or hardware resources required from device except pin connection ? program flow control go, stop, reset, step into, step over, step out, run-to-cursor ? unlimited number of user program breakpoints ? unlimited number of user data breakpoints, break on: data location read, write, or both read and write data location content equa l or not equal to a value data location content is grea ter or smaller than a value data location content is within or outside a range ? no limitation on device clock frequency ? program and debug interface (pdi) ? two-pin interface for extern al programming and debugging ? uses the reset pin and a dedicated pin ? no i/o pins required during programming or debugging ? jtag interface ? four-pin, ieee std. 1149.1 compli ant interface for prog ramming and debugging ? boundary scan capabi lities according to ieee std. 1149.1 (jtag) 31.2 overview the program and debug interface (pdi) is an atmel proprietary interface for external program- ming and on-chip debugging of a device. the pdi supports fast programming of nonvolatile memory (nvm ) spaces; flash, eepom, fuses, lock bits, and the user signature row. debug is supported through an on-chip debug syste m that offers nonintrusive, real-time debug. it does not require any software or hardware resources except for the device pin connection. using the atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. application debug can be done from a c or other high-level language source code level, as well as from an assembler and disassembler level. programming and debugging can be done through two physical interfaces. the primary one is the pdi physical layer, which is av ailable on all devices. this is a two-pin interface that uses the reset pin for the clock input (pdi_clk) and one other dedicated pin for data input and output (pdi_data). a jtag interface is also available on most devices, and this can be used for pro- gramming and d ebugging through the four-pin jtag inte rface. the jtag in terface is ieee std. 1149.1 compliant, and supports boundary scan. any external programmer or on-chip debug- ger/emulator can be directly connected to either of these interfaces. unless otherwise stated, all references to the pdi assume access through the pdi physical layer.
56 8074b?avr?02/12 xmega b3 32. pinout and pin functions the device pinout is shown in ?pinout/block diagram? on page 3 . in addition to general purpose i/o functionality, each pin can have several al ternate functions. this will depend on which peripheral is enabled and connected to the actual pin. only one of the pin functions can be used at time. 32.1 alternate pin f unction description the tables below show the notation for all pin functions available and describe its function. 32.1.1 operation/power supply 32.1.2 port interrupt functions 32.1.3 analog functions 32.1.4 lcd functions 32.1.5 timer/counter and awex functions vcc digital supply voltage avcc analog supply voltage gnd ground agnd analog ground sync port pin with full synchronous and limited asynchronous interrupt function async port pin with full syn chronous and full asynchro nous interrupt function acn analog comparator input pin n acnout analog comparator n output adcn analog to digital converter input pin n aref analog reference input pin segn lcd segment drive output n comn lcd common drive output n vlcd lcd voltage multiplier output bias2 lcd intermediate voltage 2 output (vlcd * 2/3) bias1 lcd intermediate voltage 1 output (vlcd * 1/3) caph lcd high end of flying capacitor capl lcd low end of flying capacitor ocnxls output compare channel x low side for timer/counter n ocnxhs output compare channel x high side for timer/counter n
57 8074b?avr?02/12 xmega b3 32.1.6 communication functions 32.1.7 oscillators, clock and event 32.1.8 debug/system functions scl serial clock for twi sda serial data for twi sclin serial clock in for twi when external driver interface is enabled sclout serial clock out for twi when external driver interface is enabled sdain serial data in for twi when external driver interface is enabled sdaout serial data out for twi when ex ternal driver interface is enabled xckn transfer clock for usart n rxdn receiver data for usart n txdn transmitter data for usart n ss slave select for spi mosi master out slave in for spi miso master in slave out for spi sck serial clock for spi d- data- for usb d+ data+ for usb toscn timer oscillator pin n xtaln input/output for oscillator pin n clkout peripheral clock output evout event channel 0 output rtcout rtc clock source output reset reset pin pdi_clk program and debug interface clock pin pdi_data program and debug interface data pin t c k j tag te s t c l o c k tdi jtag test data in t d o j tag te s t d a t a o u t t m s j tag te s t m o d e s e l e c t
58 8074b?avr?02/12 xmega b3 32.2 alternate pin functions the tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. the head row shows what peripheral that enable and use the alternate pin functions. for better flexibility, some alternate functions also have selectable pin locations for their func- tions, this is noted under the the first table where this apply. notes: 1. pin mapping of all tc0 can optionally be moved to high nibble of port. 2. pin mapping of all usart0 can optionally be moved to high nibble of port. 3. pins mosi and sck for all spi can optionally be swapped. 4. clkout can optionally be moved between pin 4 and 7. 5. evout can optionally be moved between pin 4 and 7. table 32-1. port b - alternate functions port b pin # interrupt adca pos/gainpos adcb pos/gainpos adcb neg adcb gainneg acb pos acb neg acb out refb jtag agnd 55 avdd 56 pb0 57 sync adc8 adc0 adc0 ac0 ac0 aref pb1 58 sync adc9 adc1 adc1 ac1 ac1 pb2 59 sync/async adc10 adc2 adc2 ac2 pb3 60 sync adc11 adc3 adc3 ac3 ac3 pb4 61 sync adc12 adc4 adc4 ac4 tms pb5 62 sync adc13 adc5 adc5 ac5 ac5 tdi pb6 63 sync adc14 adc6 adc6 ac6 ac1out tck pb7 64 sync adc15 adc7 adc7 ac7 ac0out tdo table 32-2. port c - alternate functions port c pin # interrupt tcc0 (1) awexc tcc1 tcc2 usartc0 (2) spic (3) twic extclk clockout (4) eventout (5) pc0 1 sync oc0a oc0als oc0al sda/sdain extclkc0 pc1 2 sync oc0b oc0ahs oc0bl xck0 scl/sclin extclkc1 pc2 3 sync/async oc0c oc0bls oc0cl rxd0 sdaout extclkc2 pc3 4 sync oc0d oc0bhs oc0dl txd0 sclout extclkc3 pc4 5 sync oc0cls oc1a oc0ah ss extclkc4 pc5 6 sync oc0chs oc1b oc0bh mosi extclkc5 pc6 7 sync oc0dls oc0ch miso extclkc6 rtcout pc7 8 sync oc0dhs oc0dh sck extclkc7 clk per evout table 32-3. port d - alternate functions port d pin # interrupt usbd gnd 9 vcc 10 pd0 11 sync d- pd1 12 sync d+
59 8074b?avr?02/12 xmega b3 table 32-4. program and debug functions prog pin # interrupt prog pdi 13 pdi_d reset 14 pdi_clk table 32-5. lcd lcd (1)(2) pin # interrupt (1) gpio (1) blink (1) gnd 15 vcc 16 seg24 17 sync pg0 seg23 18 sync pg1 seg22 19 sync/async pg2 seg21 20 sync pg3 seg20 21 sync pg4 seg19 22 sync pg5 seg18 23 sync pg6 seg17 24 sync pg7 seg16 25 sync pm0 seg15 26 sync pm1 seg14 27 sync/async pm2 seg13 28 sync pm3 seg12 29 sync pm4 seg11 30 sync pm5 seg10 31 sync pm6 seg9 32 sync pm7 seg8 33 seg7 34 seg6 35 seg5 35 seg4 37 seg3 38 seg2 39 seg1 40 blink seg0 41 blink gnd 42 vcc 43 bias1 44 bias2 45 vlcd 46 capl 47 caph 48 com0 49
60 8074b?avr?02/12 xmega b3 notes: 1. pin mapping of all segment terminals (segn) can be opti onnaly swapped. interrupt, gpio and blink functions will be auto - matically swapped. 2. pin mapping of all common terminals (comn)can be optionnaly swapped. com1 50 com2 51 com3 52 table 32-5. lcd (continued) lcd (1)(2) pin # interrupt (1) gpio (1) blink (1) table 32-6. port r- alternate functions port r pin # interrupt xtal tosc extclk pro 53 sync xtal2 tosc2 pr1 54 sync xtal1 tosc1 extclk
61 8074b?avr?02/12 xmega b3 33. peripheral modu le address map the address maps show the base address for each peripheral and module in xmega b3. for complete register description and summary for each peripheral module, refer to the xmega b manual. base address name description 0x0000 gpio general purpose io registers 0x0010 vport0 virtual port 0 0x0014 vport1 virtual port 1 0x0018 vport2 virtual port 2 0x001c vport3 virtual port 3 0x0030 cpu cpu 0x0040 clk clock control 0x0048 sleep sleep controller 0x0050 osc oscillator control 0x0060 dfllrc32m dfll for the 32mhz internal oscillator 0x0068 dfllrc2m dfll for the 2mhz internal oscillator 0x0070 pr power reduction 0x0078 rst reset controller 0x0080 wdt watch-dog timer 0x0090 mcu mcu control 0x00a0 pmic programmable multilevel interrupt controller 0x00b0 portcfg port configuration 0x00c0 aes aes module 0x00d0 crc crc module 0x0100 dma dma controller 0x0180 evsys event system 0x01c0 nvm non volatile memory (nvm) controller 0x0240 adcb analog to digital converter on port b 0x0390 acb analog comparator pair on port b 0x0400 rtc real time counter 0x0480 twic two wire interface on port c 0x04c0 usb usb device 0x0620 portb port b 0x0640 portc port c 0x0660 portd port d 0x06c0 portg port g 0x0760 portm port m 0x07e0 portr port r 0x0800 tcc0 timer/counter 0 on port c 0x0840 tcc1 timer/counter 1 on port c 0x0880 awexc advanced waveform extension on port c 0x0890 hiresc high resolution extension on port c 0x08a0 usartc0 usart 0 on port c 0x08c0 spic serial peripheral interface on port c 0x08f8 ircom infrared communication module 0x0d00 lcd liquid crystal display
62 8074b?avr?02/12 xmega b3 34. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd rd + rr + c z,c,n,v,s,h 1 adiw rd, k add immediate to word rd rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd rd - k - c z,c,n,v,s,h 1 sbiw rd, k subtract immediate from word rd + 1:rd rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd rd ? k z,n,v,s 1 or rd, rr logical or rd rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd rd v k z,n,v,s 1 eor rd, rr exclusive or rd rd rr z,n,v,s 1 com rd one?s complement rd $ff - rd z,c,n,v,s 1 neg rd two?s complement rd $00 - rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd rd + 1 z,n,v,s 1 dec rd decrement rd rd - 1 z,n,v,s 1 tst rd test for zero or minus rd rd ? rd z,n,v,s 1 clr rd clear register rd rd rd z,n,v,s 1 ser rd set register rd $ff none 1 mul rd,rr multiply unsigned r1:r0 rd x rr (uu) z,c 2 muls rd,rr multiply signed r1:r0 rd x rr (ss) z,c 2 mulsu rd,rr multiply signed with unsigned r1:r0 rd x rr (su) z,c 2 fmul rd,rr fractional multiply unsigned r1:r0 rd x rr<<1 (uu) z,c 2 fmuls rd,rr fractional multiply signed r1:r0 rd x rr<<1 (ss) z,c 2 fmulsu rd,rr fractional multiply signed with unsigned r1:r0 rd x rr<<1 (su) z,c 2 des k data encryption if (h = 0) then r15:r0 else if (h = 1) then r15:r0 encrypt(r15:r0, k) decrypt(r15:r0, k) 1/2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) z, eind none 2 jmp k jump pc k none 3 rcall k relative call subroutine pc pc + k + 1 none 2 / 3 (1) icall indirect call to (z) pc(15:0) pc(21:16) z, 0 none 2 / 3 (1) eicall extended indirect call to (z) pc(15:0) pc(21:16) z, eind none 3 (1)
63 8074b?avr?02/12 xmega b3 call k call subroutine pc k none 3 / 4 (1) ret subroutine return pc stack none 4 / 5 (1) reti interrupt return pc stack i 4 / 5 (1) cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd - rr z,c,n,v,s,h 1 cpc rd,rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd,k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd rr none 1 movw rd, rr copy register pair rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 lds rd, k load direct from data space rd (k) none 2 (1)(2) ld rd, x load indirect rd (x) none 1 (1)(2) ld rd, x+ load indirect and post-increment rd x (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x x - 1, rd (x) x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd (y) (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y (y) y + 1 none 1 (1)(2) mnemonics operands description operation flags #clocks
64 8074b?avr?02/12 xmega b3 ld rd, -y load indirect and pre-decrement y rd y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd (y + q) none 2 (1)(2) ld rd, z load indirect rd (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) rd none 2 (1) st x, rr store indirect (x) rr none 1 (1) st x+, rr store indirect and post-increment (x) x rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) x - 1, rr none 2 (1) st y, rr store indirect (y) rr none 1 (1) st y+, rr store indirect and post-increment (y) y rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) rr none 2 (1) st z, rr store indirect (z) rr none 1 (1) st z+, rr store indirect and post-increment (z) z rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z z - 1 none 2 (1) std z+q,rr store indirect with displacement (z + q) rr none 2 (1) lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-increment rd z (z), z + 1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z (rampz:z), z + 1 none 3 spm store program memory (rampz:z) r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z r1:r0, z + 2 none - in rd, a in from i/o location rd i/o(a) none 1 out a, rr out to i/o location i/o(a) rr none 1 push rr push register on stack stack rr none 1 (1) pop rd pop register from stack rd stack none 2 (1) xch z, rd exchange ram location temp rd (z) rd, (z), te m p none 2 las z, rd load and set ram location temp rd (z) rd, (z), te m p v ( z ) none 2 lac z, rd load and clear ram location temp rd (z) rd, (z), ($ffh ? rd) ? (z) none 2 mnemonics operands description operation flags #clocks
65 8074b?avr?02/12 xmega b3 notes: 1. cycle times for data memory access es assume internal memory accesses, and are not valid for accesses via the external r am interface. 2. one extra cycle must be added when accessing internal sram. lat z, rd load and toggle ram location temp rd (z) rd, (z), te m p (z) none 2 bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c rd(n+1), 0, rd(0) z,c,n,v 1 rol rd rotate left through carry rd(0) rd(n+1) c c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0sreg(s)1 sbi a, b set bit in i/o register i/o(a, b) 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) 0 none 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0h1 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks
66 8074b?avr?02/12 xmega b3 35. packaging information 35.1 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1.this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
67 8074b?avr?02/12 xmega b3 35.2 64m2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m2 , 64-pad, 9 x 9 x 1.0mm bod y, lead pitch 0.50mm , e 64m2 2011-10-28 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 7.50 7.65 7.80 8.90 9.00 9.10 8.90 9.00 9.10 e e2 7.50 7.65 7.80 e 0.50 bsc l 0.35 0.40 0.45 top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 0.20 0.27 0.40 2. dimension and tolerance conform to asmey14.5m-1994. 0.20 ref a3 a3 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k notes: 1. jedec standard mo-220, (saw singulation) fig. 1, vmmd. 7.65mm exposed pad, package (qfn) quad flat no lead
68 8074b?avr?02/12 xmega b3 36. electrical characteristics all typical values are measured at t = 25 c unless other temperature condition is given. all min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 36.1 absolute maximum ratings stresses beyond those listed in table 36-1 on page 68 under may cause permanent damage to the device. this is a stress rating only and f unctional operation of the device at these or other conditions beyond those indicated in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 36.2 general operating ratings the device must operate within the ratings listed in table 36-2 on page 68 in order for all other electrical characteristics and typical characteristics of the device to be guranteed and valid. table 36-1. absolute maximum ratings. symbol parameter condition min. typ. max. units vcc power supply voltage -0.3 4 v i vcc current into a vcc pin 200 ma i gnd current out of a gnd pin 200 v pin pin voltage with respect to gnd and vcc -0.5 vcc+0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 table 36-2. general operating conditions. symbol parameter condition min. typ. max. units vcc power supply voltage 1.60 3.6 v avcc 1.60 3.6 t a temperature range -40 85 c t j junction temperature -40 105 table 36-3. operating voltage and frequency symbol parameter condition min typ max units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
69 8074b?avr?02/12 xmega b3 the maximum system clock frequency of the atmel ? avr ? xmega b3 devices is depending on v cc . as shown in figure 36-1 on page 69 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 36-1. maximum frequency vs. vcc 1. 8 12 32 mhz v 2.7 3.6 1.6 safe operating area
70 8074b?avr?02/12 xmega b3 36.3 dc characteristics notes: 1. all power reduction registers set. 2. maximum limits are based on characte rization and not tested in production. table 36-4. current consumption for active and sleep modes symbol parameter condition min typ max units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 150 a v cc = 3.0v 320 1mhz, ext. clk v cc = 1.8v 350 v cc = 3.0v 700 2mhz, ext. clk v cc = 1.8v 650 800 v cc = 3.0v 1.0 1.6 ma 32mhz, ext. clk 10 15 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 4.0 a v cc = 3.0v 8.0 1mhz, ext. clk v cc = 1.8v 80 v cc = 3.0v 150 2mhz, ext. clk v cc = 1.8v 160 250 v cc = 3.0v 300 600 32mhz, ext. clk 4.7 7 ma power-down power consumption t = 25c v cc = 3.0v 0.1 1.0 a t = 85c 2.1 5 wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.2 2.5 wdt and sampled bod enabled, t = 25c v cc = 3.0v 1.3 3 wdt and sampled bod enabled, t=85c 3.1 7 power-save power consumption (2) rtc on ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.2 v cc = 3.0v 1.3 rtc on 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.8 v cc = 3.0v 0.9 rtc from low power 32.768khz tosc, t = 25c v cc = 1.8v 1.3 v cc = 3.0v 1.6 i cc power-save power consumption (2) rtc on ulp clock, wdt, sampled bod and lcd enabled, and all pixels on, t = 25c v cc = 1.8v 4.6 a v cc = 3.0v 5.2 rtc on 1.024khz low power 32.768khz tosc, lcd enabled and all pixels on t = 25c v cc = 1.8v 3.9 v cc = 3.0v 4.3 rtc from low power 32.768khz tosc, lcd enabled and all pixels on, t = 25c v cc = 1.8v 4.0 v cc = 3.0v 4.5 reset power consumption current through reset pin substracted v cc = 3.0v 420
71 8074b?avr?02/12 xmega b3 table 36-5. current consumption for modules and peripherals symbol parameter condition (1) min typ max units i cc ulp oscillator 1.0 a 32.768khz int. oscillator 26 2mhz int. oscillator 80 dfll enabled with 32.768khz int. osc. as reference 112 32mhz int. oscillator 255 dfll enabled with 32.768khz int. osc. as reference 444 pll multiplication factor = 20x 316 watchdog timer 1 bod continuous mode 126 sampled mode, include ulp oscillator 1.3 lcd (2) no pixel load contrast min all pixels off 3.0 100 pixels on 3.0 all pixels on 3.0 contrast typ all pixels off 3.3 100 pixels on 3.4 all pixels on 3.4 contrast max all pixels off 3.8 100 pixels on 3.9 all pixels on 3.9 22pf pixel load contrast typ all pixels off 3.7 all pixels on 4.3 internal 1.0v reference 100 temperature sensor 100 adc 16ksps vref = ext ref 1.3 ma currlimit = low 1.1 currlimit = medium 1.0 currlimit = high 0.9 75ksps vref = ext ref 1.7 300ksps vref = ext ref 3.1 ac 440 a dma 615kbps between i/o registers and sram 115 usart rx and tx enabled, 9600 baud 9 flash memory and eeprom programming 4.4 ma
72 8074b?avr?02/12 xmega b3 notes: 1. all parameters measured as the difference in curren t consumption between module enabled and disabled. all data at v cc =3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditiond are given. 2. lcd configuration: internal voltage generation, 32hz low power frame rate, 1/3 bias, clocked by low power 32.768khz tosc. 36.4 wake-up time from sleep modes note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 36-2 on page 72 . all peripherals and modules start execution from the first clock cycle, expect the cpu that is halted for four clock cycles before program execution starts. figure 36-2. wake-up time definition. table 36-6. device wake-up time from sleep modes with various syst em clock sources. symbol parameter condition min typ max units t wakeup wake-up time from idle, standby, and extend standby external 2mhz clock 2 s 32.768khz internal oscillator 120 2mhz internal oscillator 2 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.5 32.768khz internal oscillator 320 2mhz internal oscillator 9 32mhz internal oscillator 5 wakeup request clock output wakeup time
73 8074b?avr?02/12 xmega b3 36.5 i/o pin c haracteristics the i/o pins complies with the jedec lvttl and lvcsmos specification and the high- and low level input and ou tput voltage limits reflect or exceed this specification. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc, portd, porte and pdi must for each port not exceed 200ma tthe sum of all i oh for portg and portm must not exceed 100ma. the sum of all i oh for portr must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc, portd, porte must for each port not exceed 200ma. the sum of all i ol for portg and portm must not exceed 100ma. the sum of all i ol portr must not exceed 100ma. 3. from design simulations table 36-7. i/o pin characteristics symbol parameter condition min typ max units (1) i oh / (2) i ol i/o pin source/sink current -20 20 ma v ih high level input voltage v cc = 3.0 - 3.6v 0.6*v cc v cc +0.3 v v cc = 2.3 - 2.7v 0.6*v cc v cc +0.3 v cc = 1.6 - 2.3v 0.6*v cc v cc +0.3 v il low level input voltage v cc = 3.0 - 3.6v -0.3 0.4*v cc v cc = 2.3 - 2.7v -0.3 0.4*v cc v cc = 1.6 - 2.3v -0.3 0.4*v cc v ol output low voltage gpio v cc = 3.3v i ol = 15ma 0.4 0.76 v cc = 3.0v i ol = 10ma 0.26 0.64 v cc = 1.8v i ol = 5ma 0.17 0.46 v oh output high voltage gpio v cc = 3.3v i oh = -8ma 2.6 2.8 v cc = 3.0v i oh = -6ma 2.1 2.6 v cc = 1.8v i oh = -2ma 1.4 1.6 i in input leakage current i/o pin <0.01 1 a r p pull/buss keeper resistor 25 k r rst reset pin pull-up resistor 25 (3) t r rise time no load 4 ns slew rate limitation 7
74 8074b?avr?02/12 xmega b3 36.6 liquid crystal disp lay characteristics notes: 1. applies to static and 1/3 bias 36.7 adc characteristics table 36-8. liquid crystal display characteristics symbol parameter condition min typ max units seg segment terminal pins 0 40 com common terminal pins 0 4 f frame lcd frame frequency f(clk lcd )=32.768khz 31.25 512 hz c flying flying capacitor 100 nf contrast contrast adjustement -0.5 0 0.5 v v lcd lcd regulated voltages c flying = 0.1f 0.1f on v lcd , bias2 and bias1 pins 3 bias2 2*v lcd /3 bias1 v lcd /3 r com common output impedance com0 to com3 (1) 0.25 0.5 1 k r seg segment output impedance seg0 to seg39 (1) 248 table 36-9. power supply, reference and input range. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 r in input resistance switched 4.5 k c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m c aref reference input capacit ance static load 7 pf vin input range 0 v ref v vin conversion range differential mode, vinp - vinn -v ref v ref vin conversion range single ended unsigned mode, vinp - v v ref - v v fixed offset voltage 200 lsb
75 8074b?avr?02/12 xmega b3 table 36-10. clock and timing. symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation ( currlimit) off 16 300 ksps currlimit = low 250 currlimit = medium 150 currlimit = high 50 sampling time 1/2 clk adc cycle 0.25 5 s conversion time (latency) (res+2)/2+(gain !=0) res (resolution) = 8 or 12 610 clk adc cycles start-up time adc clock cycles 12 24 clk adc cycles adc settling time after changing reference or input mode 7 7 table 36-11. accuracy characteristics. symbol parameter condition (2) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (1) integral non-linearity differential mode 16ksps, v ref = 3v 0.5 1 lsb 16ksps, all v ref 0.8 2 300ksps, v ref = 3v 0.6 1 300ksps, all v ref 12 single ended unsigned mode 16ksps, v ref = 3.0v 0.5 1 16ksps, all v ref 1.3 2 dnl (1) differential non-linearity differential mode 16ksps, v ref = 3v 0.3 1 16ksps, all v ref 0.5 1 300ksps, v ref = 3v 0.35 1 300ksps, all v ref 0.5 1 single ended unsigned mode 16ksps, v ref = 3.0v 0.6 1 16ksps, all v ref 0.6 1 offset error differential mode 300ksps, v ref =3v -7 mv temperature drift, v ref =3v 0.01 mv/k operating voltage drift 0.16 mv/v
76 8074b?avr?02/12 xmega b3 notes: 1. maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external vref is used. gain error differential mode external reference -5 mv av cc /1.6 -5 av cc /2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv av cc /1.6 -8 av cc /2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v table 36-11. accuracy characteristics. (continued) symbol parameter condition (2) min. typ. max. units table 36-12. gain stage characteristics. symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock rate same as adc 100 1800 khz gain error 0.5x gain, normal mode -1 % 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 5 offset error, input referred 0.5x gain, normal mode 10 mv 1x gain, normal mode 5 8x gain, normal mode -20 64x gain, normal mode -126
77 8074b?avr?02/12 xmega b3 36.8 analog comparator characteristics 36.9 bandgap and internal 1.0v reference characteristics table 36-13. analog comparator characteristics. symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range 0.1 av cc - 0.1 v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 12 v hys3 hysteresis, large v cc = 1.6v - 3.6v 28 t delay propagation delay v cc = 3.0v, t= 85c 22 30 ns v cc = 1.6v - 3.6v 21 40 64-level voltage scaler integral non- linearity (inl) 0.3 0.5 lsb current source accuracy after calibration 5 % current source calibration range single mode 4 6 a current source calibration range double mode 8 12 table 36-14. bandgap and internal 1.0v reference characteristics symbol parameter condition min typ max units startup time as reference for adc 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference for adc t= 85c, after calibration 0.99 1 1.01 variation over voltage and temperature calibrated at t= 85c 2.25 %
78 8074b?avr?02/12 xmega b3 36.10 brownout detection characteristics note: 1. bod is calibrated at 85c within bod leve l 0 values, and bod level 0 is the default level. 36.11 external reset characteristics 36.12 power-on reset characteristics note: 1. both v pot- values are only valid when bod is disabled. when bod is enabled the bod is enabled, and v pot- =v pot+ table 36-15. brownout detection characteristics (1) symbol parameter condition min typ max units bod level 0 falling vcc t = 85 c, calibrated 1.5 1.6 1.72 v bod level 1 falling vcc 1.8 bod level 2 falling vcc 2.0 bod level 3 falling vcc 2.2 bod level 4 falling vcc 2.4 bod level 5 falling vcc 2.6 bod level 6 falling vcc 2.8 bod level 7 falling vcc 3.0 t bod detection time continous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.6 % table 36-16. external reset characteristics symbol parameter condition min typ max units t ext minimum reset pulse width 90 1000 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.50*v cc v v cc = 1.6 - 2.7v 0.40*v cc table 36-17. power-on reset characteristics symbol parameter condition min typ max units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.3 v pot+ por threshold voltage rising v cc 1.3 1.59
79 8074b?avr?02/12 xmega b3 36.13 flash and eeprom memory characteristics notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. 36.14 clock and oscillator characteristics 36.14.1 calibrated 32.768khz internal oscillator characteristics table 36-18. endurance and data retention symbol parameter condi tion min typ max units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 100k cycle 85c 100k data retention 25c 100 year 55c 25 table 36-19. programming time symbol parameter condition min typ (1) max units chip erase 128kb flash, eeprom (2) 75 ms 64kb flash, eeprom (2) 55 flash page erase 4 page write 4 page writeautomatic page erase and write 8 eeprom page erase 4 page write 4 page writeautomatic page erase and write 8 table 36-20. calibrated 32.768khz internal oscillator characteristics symbol parameter condition min typ max units frequency 32.768 khz factory calibrated accuracy t = 85 c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5
80 8074b?avr?02/12 xmega b3 36.14.2 calibrated 2mhz rc internal oscillator characteristics 36.14.3 calibrated and tunable 32mhz internal oscillator characteristics 36.14.4 32khz internal ulp oscillator characteristics 36.14.5 phase locked loop (pll) characteristics note: 1. the maximum output frequency vs. supply voltage is linear between 1.8v and 2.7v, and can never be higher than 4 times the maximum cpu frequency table 36-21. calibrated 2mhz internal oscillator characteristics symbol parameter condition min typ max units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.2 mhz factory calibrated frequency 2.0 factory calibration accuracy t = 85 c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.22 table 36-22. calibrated 32mhz internal oscillator characteristics symbol parameter condition min typ max units frequency range dfll can tune to this frequency over voltage and temperature 30 35 mhz factory calibrated frequency 32 factory calibration accuracy t = 85 c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.23 table 36-23. 32khz internal ulp osc illator characteristics symbol parameter condition min typ max units factory calibrated frequency 32 khz factory calibration accuracy t = 85 c, v cc = 3.0v -12 12 % table 36-24. phase locked loop characteristics symbol parameter condition min typ max units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.60v 20 32 v cc = 2.70v 20 128 start-up time 23 100 s re-lock time 20 50
81 8074b?avr?02/12 xmega b3 36.14.6 external clock characteristics figure 36-3. external clock drive waveform note: 1. the maximum frequency vs. supply voltage is linear between 1. 8v and 2.7v, and the same applies for all other parameters with supply voltage conditions. t ch t cl t ck t ch v il1 v ih1 t cr t cf table 36-25. external clock used as system clock without prescaling symbol parameter condition min typ max units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 v cc = 2.7 - 3.6v 3 t ck change in period from one clock cycle to the next 10 %
82 8074b?avr?02/12 xmega b3 notes: 1. system clock prescalers must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.8v and 2.7v, and the same applies for all other parameters with supply voltage conditions 36.14.7 external 16mhz crystal oscillator and xosc characteristics table 36-27. external 16mhz crystal oscilla tor and xosc characteristics. table 36-26. external clock with prescaler (1) for system clock symbol parameter condition min typ max units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) 1.5 t cf fall time (for maximum frequency) 1.5 t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0, frqrange=0 0 ns xoscpwr=0, frqrange=1, 2, or 3 0 xoscpwr=1 0 long term jitter xoscpwr=0, frqrange=0 0 xoscpwr=0, frqrange=1, 2, or 3 0 xoscpwr=1 0 frequency error xoscpwr=0, frqrange=0 0.03 % xoscpwr=0, frqrange=1 0.03 xoscpwr=0, frqrange=2 or 3 0.03 xoscpwr=1 0.03 duty cycle xoscpwr=0, frqrange=0 50 xoscpwr=0, frqrange=1 50 xoscpwr=0, frqrange=2 or 3 50 xoscpwr=1 50
83 8074b?avr?02/12 xmega b3 note: 1. numbers for negative impedance are not tested but guaranteed from design and characterization. r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 44k 1mhz crystal, cl=20pf 67k 2mhz crystal, cl=20pf 67k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 82k 8mhz crystal 1500 9mhz crystal 1500 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 2700 9mhz crystal 2700 12mhz crystal 1000 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 3600 12mhz crystal 1300 16mhz crystal 590 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 390 12mhz crystal 50 16mhz crystal 10 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 1500 12mhz crystal 650 16mhz crystal 270 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 1000 16mhz crystal 440 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 1300 16mhz crystal 590 start-up time xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 1.0 ms xoscpwr=0, frqrange=1 2mhz crystal, cl=20pf 2.6 xoscpwr=0, frqrange=2 8mhz crystal, cl=20pf 0.8 xoscpwr=0, frqrange=3 12mhz crystal, cl=20pf 1.0 xoscpwr=1, frqrange=3 16mhz crystal, cl=20pf 1.4 c xtal1 parasitic capacitance 5.9 pf c xtal2 parasitic capacitance 8.3 c load parasitic capacitance load 3.5 symbol parameter condition min. typ. max. units
84 8074b?avr?02/12 xmega b3 36.14.8 external 32.768khz crystal oscillator and tosc characteristics note: 1. see figure 36-4 on page 84 for definition figure 36-4. tosc input capacitance the input capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. table 36-28. external 32.768khz crystal osc illator and tosc characteristics symbol parameter condi tion min typ max units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k crystal load capacitance 9.0pf 35 crystal load capacitance 12.0pf 28 c in_tosc input capacitance between tosc pins normal mode 3.5 pf low power mode 3.5 recommended safety factor capacitance load matched to crystal specification 3 long term jitter (sit) 0% c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
85 8074b?avr?02/12 xmega b3 36.15 spi characteristics figure 36-5. spi interface requirements in master mode figure 36-6. spi timing requirements in slave mode msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
86 8074b?avr?02/12 xmega b3 table 36-29. spi timing characteristics and requirements symbol parameter condition min typ max units t sck sck period master (see table 21-4 in xmega b manual) ns t sckw sck high/low width master 0.5*sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 11 t mih miso hold after sck master 0 t mos mosi setup sck master 0.5*sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4*t clk per t ssckw sck high/low width slave 2*t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave t clk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8
87 8074b?avr?02/12 xmega b3 36.16 two-wire interface characteristics table 2-1 describes the requirements for devices connected to the two wire serial bus. the xmega two-wire interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 36-7 . figure 36-7. two-wire interface bus timing t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto table 36-30. two wire serial bus characteristics symbol parameter condition min typ max units v ih input high voltage 0.7*v cc v cc +0.5 v v il input low voltage -0.5 0.3*v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) 0 v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20+0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20+0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) >max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl 100khz f scl > 100khz t hd;sta hold time (repeated) start condition f scl 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl 100khz 4.7 f scl > 100khz 0.6 v cc 0.4 v ? 3 ma ---------------------------- 100 ns c b --------------- - 300 ns c b --------------- -
88 8074b?avr?02/12 xmega b3 notes: 1. required only for f scl > 100khz 2. c b = capacitance of one bus line in pf 3. f per = peripheral clock frequency t hd;dat data hold time f scl 100khz 0 3.5 s f scl > 100khz 0 0.9 t su;dat data setup time f scl 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl 100khz 4.7 f scl > 100khz 1.3 table 36-30. two wire serial bus characteristics (continued) symbol parameter condition min typ max units
89 8074b?avr?02/12 xmega b3 37. typical characteristics 37.1 current consumption 37.1.1 active mode supply current figure 37-1. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 37-2. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . , 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v 100 200 300 400 500 600 700 800 900 1000 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ a] 3.6 v 3.0 v 2.7 v 0 2 4 6 8 10 12 14 04 8 12 16 20 24 2 8 32 fre qu ency [mhz] icc[ma] 1. 8v 2.2 v
90 8074b?avr?02/12 xmega b3 figure 37-3. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 37-4. active mode supply current vs. v cc . f sys = 32mhz internal oscillator . 8 5c 25c -40c 500 700 900 1100 1300 1500 1700 1900 2100 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a] 8 5 c 25 c -40 c 8 000 8 750 9500 10250 11000 11750 12500 13250 14000 2.7 2. 8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [ v ] icc[ a]
91 8074b?avr?02/12 xmega b3 37.1.2 idle mode supply current figure 37-5. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 37-6. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.6 v 3.0 v 2.7 v 2.2 v 1. 8v 1.6 v 0 20 40 60 8 0 100 120 140 160 1 8 0 0.10.20.30.40.50.60.70. 8 0.9 1 fre qu ency [mhz] icc[ a] 3.6 v 3.0 v 2.7 v 0 1 2 3 4 5 6 04 8 12 16 20 24 2 8 32 fre qu ency [mhz] icc[ma] 1. 8v 2.2 v
92 8074b?avr?02/12 xmega b3 figure 37-7. idle mode supply current vs. v cc . f sys = 32.768khz inter nal oscillator . figure 37-8. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 8 5c 25c -40c 27 27.75 2 8 .5 29.25 30 30.75 31.5 32.25 33 33.75 34.5 1.6 1. 8 22.22.42.62. 8 3 3.2 3.4 3.6 v cc [ v ] icc[ a] 8 5c 25c -40c 150 175 200 225 250 275 300 325 350 375 400 425 450 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] icc [ a]
93 8074b?avr?02/12 xmega b3 figure 37-9. idle mode current vs. v cc . f sys = 32mhz internal oscillator . 37.1.3 power-down mode supply current figure 37-10. power-down mode supp ly current vs. v cc . all functions disabled . 8 5 c 25 c -40 c 1 8 00 2300 2 8 00 3300 3 8 00 4300 4 8 00 5300 5 8 00 1.6 1. 8 22.22.42.62. 8 33.23.43.6 v cc [ v ] icc [a] 8 5c 25c -40c 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 1.6 1. 8 2 2.2 2.4 2.6 2. 8 33.23.43.6 v cc [ v ] i cc [ a]
94 8074b?avr?02/12 xmega b3 figure 37-11. power-down mode supp ly current vs. v cc . watchdog and sampled bod enabled . 37.2 i/o pin c haracteristics 37.2.1 pull-up figure 37-12. i/o pin pull-up resistor current vs. input voltage. v cc = 1.8v . 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 1.6 1. 8 2 2.2 2.4 2.6 2. 8 33.23.43.6 v cc [ v ] i cc [ a] 8 5c 25c -40c 0 10 20 30 40 50 60 70 8 0 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v pi n [ v ] i pi n [ a]
95 8074b?avr?02/12 xmega b3 figure 37-13. i/o pin pull-up resistor current vs. input voltage. v cc = 3.0v . figure 37-14. i/o pin pull-up resistor current vs. pin voltage. v cc = 3.3v . 8 5c 25c -40c 0 20 40 60 8 0 100 120 140 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 v pi n [ v ] i pi n [ a] 8 5c 25c -40c 0 20 40 60 8 0 100 120 140 160 0 0.35 0.7 1.05 1.4 1.75 2.1 2.45 2. 8 3.15 3.5 v pi n [ v ] i pi n [ a]
96 8074b?avr?02/12 xmega b3 37.2.2 output voltage vs. sink/source current figure 37-15. i/o pin output voltage vs. source current. v cc = 1.8v . figure 37-16. i/o pin output voltage vs. source current. v cc = 3.0v . 8 5c 25c -40c 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 1.9 -6 -5.4 -4. 8 -4.2 -3.6 -3 -2.4 -1. 8 -1.2 -0.6 0 i pi n [ma] v pi n [ v ] 8 5c 25c -40c 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 -20 -1 8 -16 -14 -12 -10 - 8 -6 -4 -2 0 i pi n [ma] v pi n [ v ]
97 8074b?avr?02/12 xmega b3 figure 37-17. i/o pin output voltage vs. source current. v cc = 3.3v . figure 37-18. i/o pin output voltage vs. sink current. v cc = 1.8v . 8 5c 25c -40c 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 -20 -1 8 -16-14-12-10 - 8 -6 -4 -2 0 i pi n [ma] v pi n [ v ] 8 5c 25c -40c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 0246 8 10 12 14 16 1 8 20 i pi n [ma] v pi n [ v ]
98 8074b?avr?02/12 xmega b3 figure 37-19. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 37-20. i/o pin output voltage vs. sink current. v cc = 3.3v . 8 5c 25c -40c 0 0.06 0.12 0.1 8 0.24 0.3 0.36 0.42 0.4 8 0.54 0.6 0246 8 10 12 14 16 1 8 20 i pi n [ma] v pi n [ v ] 8 5c 25c -40c 0 0.06 0.12 0.1 8 0.24 0.3 0.36 0.42 0.4 8 0.54 0.6 0246 8 10 12 14 16 1 8 20 i pi n [ma] v pi n [ v ]
99 8074b?avr?02/12 xmega b3 37.2.3 thresholds and hysteresis figure 37-21. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 37-22. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 8 5c 25c -40c 0. 8 1 1.2 1.4 1.6 1. 8 1.6 1. 8 2 2.2 2.4 2.6 2. 8 33.23.43.6 v cc [ v ] v threshold [ v ] 8 5c 25c -40c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v treshold [ v ]
100 8074b?avr?02/12 xmega b3 figure 37-23. i/o pin input hysteresis vs. v cc . 37.3 adc characteristics figure 37-24. inl error vs. external v ref . t = 25 c, v cc = 3.6v, external reference . 8 5c 25c -40c 100 150 200 250 300 350 v cc [ v ] v hysteresis [m v ] 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 3.2 3.4 3.6 differential mode single-ended signed mode single-ended u nsigned mode 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 1.0 1.2 1.4 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 v ref [ v ] i n l[lsb]
101 8074b?avr?02/12 xmega b3 figure 37-25. inl error vs. sample rate. t = 25 c, v cc = 3.6v, v ref = 3.0v external . figure 37-26. inl error vs. input code. differential mode single-ended signed mode single-ended u nsigned mode 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 adc sample rate [ksps] i n l[lsb] 50 100 150 200 250 300 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 0 512 1024 1536 204 8 2560 3072 35 8 44096 adc inp u t code i n l[lsb]
102 8074b?avr?02/12 xmega b3 figure 37-27. dnl error vs. external v ref . t = 25 c, v cc = 3.6v, external reference . figure 37-28. dnl error vs. sample rate. t = 25 c, v cc = 3.6v, v ref = 3.0v external . differential mode single-ended signed mode single-ended u nsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 1.0 1.2 1.4 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 v ref [ v ] d n l [lsb] differential mode single-ended signed mode single-ended u nsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 50 100 150 200 250 300 adc sample rate [ksps] d n l [lsb]
103 8074b?avr?02/12 xmega b3 figure 37-29. dnl error vs. input code. figure 37-30. gain error vs. v ref . t = 25 c, v cc = 3.6v, adc sample rate = 300ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0. 8 1 0 512 1024 1536 204 8 2560 3072 35 8 4 4096 adc inp u t code d n l [lsb] differential mode single-ended signed mode single-ended u nsigned mode -15 -14 -13 -12 -11 -10 -9 - 8 -7 -6 -5 1.0 1.2 1.4 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 v ref [ v ] gain error [m v ]
104 8074b?avr?02/12 xmega b3 figure 37-31. gain error vs. v cc . t = 25 c, v ref = external 1.0v, adc sample rate = 300ksps . figure 37-32. offset error vs. v ref . t = 25 c, v cc = 3.6v, adc sample rate = 300ksps . differential mode single-ended signed mode single-ended u nsigned mode -9 - 8 -7 -6 -5 -4 -3 -2 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 3.2 3.4 3.6 v cc [ v ] gain error [m v ] differential mode 7.0 7.2 7.4 7.6 7. 8 8 .0 8 .2 8 .4 8 .6 8 . 8 9.0 9.2 9.4 1.0 1.2 1.4 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 v ref [ v ] offset error [m v ]
105 8074b?avr?02/12 xmega b3 figure 37-33. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 37-34. offset error vs. v cc . t = 25 c, v ref = external 1.0v, adc sample rate = 300ksps. differential mode single-ended signed mode single-ended u nsigned mode -13 -12 -11 -10 -9 - 8 -7 -6 -5 -4 -3 -45-35-25-15-5 5 15253545556575 8 5 temperat u re [c] gain error [m v ] differential mode 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8 .00 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 3.2 3.4 3.6 v cc [ v ] offset error [m v ]
106 8074b?avr?02/12 xmega b3 37.4 analog comparat or characteristics figure 37-35. analog comparator hysteresis vs. v cc . high-speed mode, small hysteresis . figure 37-36. analog comparator hysteresis vs. v cc . high-speed mode, large hysteresis . 6 7 8 9 10 11 12 13 14 15 16 1.6 1. 8 2 2.2 2.4 2.6 2. 8 33.23.43.6 v hyst [m v ] 8 5oc -40 oc 25oc v cc [ v ] -40c 25c 8 5c 16 1 8 20 22 24 26 2 8 30 32 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v hyst [m v ] v cc [ v ]
107 8074b?avr?02/12 xmega b3 figure 37-37. analog comparator propagation delay vs. v cc . high speed mode . figure 37-38. analog comparator current consumption vs. v cc . high-speed mode. 8 5c 25c - 40c 16 1 8 20 22 24 26 2 8 30 32 34 1.6 1. 8 22.22.42.62. 8 3 3.2 3.4 3.6 v cc [ v ] t pd [ns] 8 5c 25c -40c 150 170 190 210 230 250 270 290 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cm [ v ] mod u le cons u mption [ a]
108 8074b?avr?02/12 xmega b3 figure 37-39. analog comparator voltage scaler vs. scalefac. t = 25 c . figure 37-40. analog comparator offset voltage vs. common mode voltage. high-speed mode. 3.6 v 3.3 v 3.0 v 2.7 v 1. 8v 1.6 v 0 0.5 1 1.5 2 2.5 3 3.5 4 0 7 14 21 2 8 35 42 49 56 63 scalefac v scale [ v ] -40c 25c 8 5c 0 2 4 6 8 10 12 14 16 1 8 20 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 v offset [m v ] v cc [ v ]
109 8074b?avr?02/12 xmega b3 figure 37-41. analog comparator current source vs. calibration. v cc = 3.0v, double mode . 37.5 internal 1.0v re ference characteristics figure 37-42. adc/dac internal 1.0v reference vs. temperature. 8 5c 25c -40c 8 8 .5 9 9.5 10 10.5 11 11.5 12 01234567 8 9101112131415 currcaliba[3..0] icurre n tsource [ a] 3.0 v 2.7 v 1. 8v 0.99 8 1 1.002 1.004 1.006 1.00 8 1.01 1.012 -40-30-20-100 10203040506070 8 0 temperat u re [c] bandgap v oltage [ v ]
110 8074b?avr?02/12 xmega b3 37.6 bod characteristics figure 37-43. bod current consumption vs. v cc . continuous mode, bod level = 1.6v . figure 37-44. bod current consumption vs. v cc . sampled mode, bod level = 1.6v . 8 5c 25c -40c 8 0 90 100 110 120 130 140 150 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] iccglo b al [ a] 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] iccglo b al [ a] 8 5c 25c -40c
111 8074b?avr?02/12 xmega b3 figure 37-45. bod thresholds vs. temperature. bod level = 1.6v . figure 37-46. bod thresholds vs. temperature. bod level = 2.2v . rising v cc falling v cc 1.604 1.606 1.60 8 1.61 1.612 1.614 1.616 1.61 8 1.62 1.622 1.624 1.626 -40-30-20-100 10203040506070 8 0 temperat u re [c] v bot [ v ] 2.305 2.31 2.315 2.32 2.325 2.33 2.335 2.34 2.345 2.35 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] v bot [ v ] rising v cc falling v cc
112 8074b?avr?02/12 xmega b3 figure 37-47. bod thresholds vs. temperature. bod level = 3.0v . 37.7 external reset characteristics figure 37-48. minimum reset pin pulse width vs. v cc . rising v cc falling v cc 3 3.01 3.02 3.03 3.04 3.05 3.06 3.07 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 0 temperat u re [c] v bot [ v ] 8 5c 25c -40c 8 0 90 100 110 120 130 140 1.6 1. 8 2 2.2 2.4 2.6 2. 8 33.23.43.6 v cc [ v ] t rst [ns]
113 8074b?avr?02/12 xmega b3 figure 37-49. reset pin pull-up resistor current vs. reset pin voltage. v cc = 1.8v . figure 37-50. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.0v . 8 5c 25c -40c 0 10 20 30 40 50 60 70 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset [ v ] i reset [ a] 8 5c 25c -40c 0 20 40 60 8 0 100 120 140 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 v reset [ v ] i reset [ a]
114 8074b?avr?02/12 xmega b3 figure 37-51. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.3v . figure 37-52. reset pin input threshold voltage vs. v cc . v ih - reset pin read as ?1? . 0 20 40 60 8 0 100 120 140 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 3.3 v reset [ v ] i reset [ a] 8 5c 25c -40c 8 5c 25c -40c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 1.6 1. 8 2 2.2 2.4 2.6 2. 8 33.23.43.6 v cc [ v ] v threshold [ v ]
115 8074b?avr?02/12 xmega b3 figure 37-53. reset pin input threshold voltage vs. v cc . v il - reset pin read as ?0? . 8 5 c 25 c -40 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ]
116 8074b?avr?02/12 xmega b3 37.8 oscillator characteristics 37.8.1 32.768khz internal oscillator figure 37-54. 32.768khz internal oscillato r frequency vs. temperature. figure 37-55. 32.768khz ulp internal oscilla tor frequency vs. temperature. 3.6 v 3.0 v 2.7 v 2.2 v 1. 8v 1.6 v 32.73 32.74 32.75 32.76 32.77 32.7 8 32.79 32. 8 32. 8 1 32. 8 2 32. 8 3 -40-30-20-100 10203040506070 8 0 temperat u re [c] fre qu ency [khz] 3.6 v 3.0 v 2.7 v 1. 8v 1.6 v 31000 31500 32000 32500 33000 33500 34000 34500 35000 35500 36000 -40-30-20-100 10203040506070 8 0 temperat u re [c] fre qu ency [hz]
117 8074b?avr?02/12 xmega b3 figure 37-56. 32.768khz internal oscillato r calibration step size. t = -40 c to 85 c, v cc = 3v . figure 37-57. 32.768khz internal oscillator frequency vs. calibration value. v cc = 3.0v, t = 25c . 8 5c 25c -40c -0.045 -0.04 -0.035 -0.03 -0.025 -0.02 -0.015 -0.01 -0.005 0.000 0.005 0.01 032649612 8 160 192 224 256 rc32kcal[7..0] step size: f [khz] 3.0 v 20 25 30 35 40 45 50 55 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 rc32kcal[7..0] fre qu ency [khz]
118 8074b?avr?02/12 xmega b3 37.8.2 2mhz internal oscillator figure 37-58. 2mhz internal oscillator frequency vs. temperature. dfll disabled . figure 37-59. 2mhz internal oscillator frequency vs. temperature. dfll enabled . 3.6 v 3.0 v 2.7 v 2.2 v 1. 8 v 1.6 v 1.96 1.9 8 2.00 2.02 2.04 2.06 2.0 8 2.1 2.12 2.14 2.16 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz] 3.6 v 3.0 v 2.7 v 2.2 v 1. 8 v 1.6 v 1.999 2.000 2.001 2.002 2.003 2.004 2.005 2.006 -40-30-20-100 10203040506070 8 0 temperat u re [c] fre qu ency [mhz]
119 8074b?avr?02/12 xmega b3 figure 37-60. 2mhz internal oscillator ca la calibration step size. v cc = 3v . figure 37-61. 2mhz internal oscillator ca lb calibration step size. v cc = 3v, dfll enabled . 8 5 c 25 c -40 c -0.27 -0.26 -0.25 -0.24 -0.23 -0.22 -0.21 -0.2 -0.19 -0.1 8 -0.17 -0.16 -0.15 -0.14 0 10203040506070 8 0 90 100 110 120 130 dfllrc2mcala step error [ % ] 8 5c 25c -40c -0.255 -0.245 -0.235 -0.225 -0.215 -0.205 -0.195 -0.1 8 5 -0.175 -0.165 -0.155 0 7 14 21 2 8 35 42 49 56 63 dfllrc2mcalb step error [ % ]
120 8074b?avr?02/12 xmega b3 37.8.3 32mhz internal oscillator figure 37-62. 32mhz internal oscillator frequency vs. temperature. dfll disabled . figure 37-63. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 3.6 v 3.0 v 2.7 v 2.2 v 1. 8v 1.6 v 31 31.5 32 32.5 33 33.5 34 34.5 35 35.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz] 3.3 v 3.0 v 2.7 v 2.2 v 1. 8v 1.6 v 31.96 31.9 8 32 32.02 32.04 32.06 32.0 8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz]
121 8074b?avr?02/12 xmega b3 figure 37-64. 32mhz internal oscillator ca la calibration step size. v cc = 3.0v . figure 37-65. 32mhz internal oscillator ca lb calibration step size. v cc = 3.0v, cala = mid value . 8 5c 25c -40c -0.3 -0.2 8 -0.26 -0.24 -0.22 -0.2 -0.1 8 -0.16 -0.14 -0.12 -0.1 0 10203040506070 8 0 90 100 110 120 130 dfllrc32mcala step error [ % ] 8 5c 25c -40c -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0 8 16 24 32 40 4 8 56 64 dfllrc32mcalb step size: step error [ % ]
122 8074b?avr?02/12 xmega b3 figure 37-66. 32mhz internal oscilla tor frequency vs. cala calibration value. v cc = 3.0v . figure 37-67. 32mhz internal oscilla tor frequency vs. calb calibration value. v cc = 3.0v, dfll enabled . 8 5c 25c -40c 36 3 8 40 42 44 46 4 8 50 52 54 56 0 8 16 24 32 40 4 8 56 64 72 8 0 88 96 104 112 120 12 8 dfllrc32mcala fre qu ency [mhz] 8 5c 25c -40c 20 25 30 35 40 45 50 55 60 65 70 0 7 14 21 2 8 35 42 49 56 63 dfllrc32mcalb fre qu ency [mhz]
123 8074b?avr?02/12 xmega b3 37.8.4 32mhz internal oscillator calibrated to 48mhz figure 37-68. 48mhz internal oscillator frequency vs. temperature. dfll disabled. figure 37-69. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 3.6 v 3.0 v 2.7 v 2.2 v 1. 8v 1.6 v 46 47 4 8 49 50 51 52 53 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz] 3.6 v 3.0 v 2.7 v 2.2 v 1. 8v 1.6 v 47.92 47.94 47.96 47.9 8 4 8 4 8 .02 4 8 .04 4 8 .06 4 8 .0 8 4 8 .1 4 8 .12 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz]
124 8074b?avr?02/12 xmega b3 figure 37-70. 32mhz internal oscillator ca la calibration step size. using 48mhz calibration value from signature row, v cc = 3.0v . figure 37-71. 48mhz internal oscilla tor frequency vs. cala calibration value. v cc = 3.0v . 8 5c 25c -40c -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0. 8 0 0 8 16 24 32 40 4 8 56 64 72 8 0 88 96 104 112 120 12 8 cala step size: step error [ % ] 8 5c 25c -40c 40 42 44 46 4 8 50 52 54 56 5 8 60 0 8 16 24 32 40 4 8 56 64 72 8 0 88 96 104 112 120 12 8 cala fre qu ency [mhz]
125 8074b?avr?02/12 xmega b3 37.9 pdi characteristics figure 37-72. maximum pdi frequency vs. v cc . 8 5c 25c -40c 17.0 17.5 1 8 .0 1 8 .5 19.0 19.5 20.0 20.5 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] fmin [khz]
126 8074b?avr?02/12 xmega b3 37.10 lcd characteristics figure 37-73. i cc vs. frame rate 32hz low p ower frame rate from 32.768khz tosc, w/ and w/o pixel load, v cc = 1.8v, t = 25c figure 37-74. i cc vs. frame rate 32hz low p ower frame rate from 32.768khz tosc, w/ and w/o pixel load, v cc = 3.0v, t = 25c 22pf all pixels off 0pf all pixels off 0pf all pixels o n 22pf all pixels o n 3 4 5 6 7 8 9 10 11 32 64 96 12 8 160 192 224 256 frame rate[hz] i cc [ a] 22pf all pixels off 22pf 100 pixels o n 22pf all pixels o n 0pf all pixels off 0pf 100 pixels o n 0pf all pixels o n 3 4 5 6 7 8 9 10 11 12 13 32 64 96 12 8 160 192 224 256 frame rate[hz] i cc [ a]
127 8074b?avr?02/12 xmega b3 figure 37-75. i cc vs. frame rate 0pf load figure 37-76. i cc vs. contrast 32hz low power frame rate from 32.768khz tosc, w/o pixel load, v cc = 1.8v -40 c 25 c 8 5c 3 5 7 9 11 13 15 32 64 96 12 8 160 192 224 256 frame rate[hz] i cc [ a ] 8 5c -40c 25c 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 -32 -23 -14 -5 4 13 22 31 contrast i cc [a]
128 8074b?avr?02/12 xmega b3 figure 37-77. i cc vs. contrast 32hz low power frame rate from 32.768khz tosc, w/o pixel load, v cc = 3.0v figure 37-78. psave lcd lp 32hz vs. temperature 8 5c -40c 25c 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 -32 -23 -14 -5 4 13 22 31 contrast i cc [a] 3.6 v 3.0 v 2.2 v 1. 8v 1.6 v 2 2.2 2.4 2.6 2. 8 3 3.2 -40-30-20-100 10203040506070 8 0 temperat u re [c] iccmod u lecons u mption [ a]
129 8074b?avr?02/12 xmega b3 figure 37-79. psave lcd lp 32hz vs. temperature rtc, wdt, bod sampled figure 37-80. psave vs. temperature rtc, wdt, bod sampled . 3.6 v 3.0 v 2.2 v 1. 8v 1.6 v 2.0 2.2 2.4 2.6 2. 8 3.0 3.2 3.4 3.6 -40-30-20-100 10203040506070 8 0 temperat u re [c] iccmod u lecons u mption [ a] 3.6 v 3.0 v 2.2 v 1. 8v 1.6 v 0.15 0.175 0.2 0.225 0.25 0.275 0.3 -40-30-20-100 10203040506070 8 0 temperat u re [c] iccmod u lecons u mption [ a]
130 8074b?avr?02/12 xmega b3 38. errata 38.1 atxmega64b3, atxmega128b3 38.1.1 rev. c ? jtag revision ? awex fault protection restore is not do ne correct in pattern generation mode 1. jtag revision is unchanged between rev. b and rev. c 2. awex fault protection restore is not done correctly in pattern generation mode when a fault is detected the outoven register is cleared, and when fault condition is cleared, outoven is restored according to the corresponding enabled dti channels. for common waveform channel mode (cwcm), this has no effect as the outoven is correct after restoring from fault. for pattern generation mode (pgm), outoven should instead have been restored according to the dtilsbuf register. problem fix/workaround for cwcm no workaround is required. for pgm in latched mode, disable the dti c hannels before returning from the fault condi- tion. then, set correct outoven value and enable the dti channels, before the direction (dir) register is written to enable the correct outputs again. for pgm in cycle-by-cycle mode there is no workaround 38.1.2 rev. b not sampled. 38.1.3 rev. a ? power down consumption ? adc convertion error when x0.5 gain is used 1. power down consumption after reset, when system enters in power dow n or when adc is dis abled, extra power con- sumption is drawn. problem fix/workaround set adc to a configuration different from differential mode. 2. adc convertion error when x0.5 gain is used when the gain is set to x0.5, the conversion result is similar to the gain setting x1. problem fix/workaround there is no workaround.
131 8074b?avr?02/12 xmega b3 39. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 39.1 8074b ?02/12 39.2 8074a ? 10/11 1. updated the table 7-2 on page 16 . the page size (words) for atxmega128b1 changed from 256 to 128. 2. udpated all ?electrical characteristics? on page 68 . 3. udpated all ?typical characteristics? on page 89 . 4. udpated ?errata? on page 130 . 1. initial revision.
i 8074b?avr?02/12 xmega b3 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 ordering information .......... .............. ............... .............. .............. ............ 2 2 pinout/block diagram ......... .............. ............... .............. .............. ............ 3 3 overview ............ ................ ................ ............... .............. .............. ............ 4 3.1block diagram ...........................................................................................................6 4 resources .............. .............. .............. ............... .............. .............. ............ 7 4.1recommended reading .............................................................................................7 5 capacitive touch sensing ................. ............... .............. .............. ............ 7 6 avr cpu ............ ................ ................ ............... .............. .............. ............ 8 6.1features ................................................................................................................... .8 6.2overview ................................................................................................................... 8 6.3architectural overview ..............................................................................................8 6.4alu - arithmetic logic unit .......................................................................................9 6.5program flow ..........................................................................................................10 6.6status register ........................................................................................................10 6.7stack and stack pointer ..........................................................................................10 6.8register file ............................................................................................................11 7 memories ............... .............. .............. ............... .............. .............. .......... 12 7.1features ..................................................................................................................1 2 7.2overview .................................................................................................................12 7.3flash program memory ...........................................................................................13 7.4fuses and lock bits ................................................................................................14 7.5data memory ...........................................................................................................14 7.6eeprom ............. ................ ................ ................ ................. ............ ............. ..........15 7.7i/o memory ..............................................................................................................15 7.8data memory and bus arbitration ...........................................................................15 7.9memory timing ........................................................................................................15 7.10device id and revision .........................................................................................16 7.11jtag disable ........................................................................................................16 7.12i/o memory protection ..........................................................................................16 7.13flash and eeprom page si ze ............. ................ ............. ............ ............. ..........16 8 dmac ? direct memory acce ss controller .............. ................. .......... 17
ii 8074b?avr?02/12 xmega b3 8.1features ..................................................................................................................1 7 8.2overview .................................................................................................................17 9 event system ........ .............. .............. ............... .............. .............. .......... 18 9.1features ..................................................................................................................1 8 9.2overview .................................................................................................................18 10 system clock and clock options ................ ................. .............. .......... 20 10.1features ................................................................................................................20 10.2overview ...............................................................................................................20 10.3clock sources .......................................................................................................21 11 power management and sleep modes ........ ................. .............. .......... 24 11.1features ................................................................................................................24 11.2overview ...............................................................................................................24 11.3sleep modes .........................................................................................................24 12 system control and reset .... .............. .............. .............. .............. ........ 26 12.1features ................................................................................................................26 12.2overview ...............................................................................................................26 12.3reset sequence ....................................................................................................26 12.4reset sources .......................................................................................................27 13 wdt ? watchdog timer ......... .............. .............. .............. .............. ........ 28 13.1features ................................................................................................................28 13.2overview ...............................................................................................................28 14 interrupts and programmabl e multilevel interrupt c ontroller ........... 29 14.1features ................................................................................................................29 14.2overview ...............................................................................................................29 14.3interrupt vectors ....................................................................................................29 15 i/o ports ............... ................ .............. ............... .............. .............. .......... 31 15.1features ................................................................................................................31 15.2overview ...............................................................................................................31 15.3output driver .........................................................................................................32 15.4input sensing .........................................................................................................34 15.5alternate port functions ........................................................................................34 16 t/c ? 16-bit timer/counte r type 0 and 1 .................. ................. .......... 35 16.1features ................................................................................................................35
iii 8074b?avr?02/12 xmega b3 16.2overview ...............................................................................................................35 17 tc2 ?16-bit timer/counter type 2 .......... ................. ................ ............. 37 17.1features ................................................................................................................37 17.2overview ...............................................................................................................37 18 awex ? advanced waveform ex tension ........... .............. ............ ........ 38 18.1features ................................................................................................................38 18.2overview ...............................................................................................................38 19 hi-res ? high resolut ion extension ......... ................ ................. .......... 39 19.1features ................................................................................................................39 19.2overview ...............................................................................................................39 20 rtc ? 16-bit real-time counter ............. ................. ................ ............. 40 20.1features ................................................................................................................40 20.2overview ...............................................................................................................40 21 usb ? universal serial bus interface ..... ................. ................ ............. 41 21.1features ................................................................................................................41 21.2overview ...............................................................................................................41 22 twi ? two wire interface ... .............. ............... .............. .............. .......... 43 22.1features ................................................................................................................43 22.2overview ...............................................................................................................43 23 spi ? serial peripheral interface ........... .............. .............. ............ ........ 45 23.1features ................................................................................................................45 23.2overview ...............................................................................................................45 24 usart ............. ................. ................ ................. .............. .............. .......... 46 24.1features ................................................................................................................46 24.2overview ...............................................................................................................46 25 ircom ? ir communication module ......... ................ ................. .......... 47 25.1features ................................................................................................................47 25.2overview ...............................................................................................................47 26 aes and des crypto engine .... ................. ................ ................. .......... 48 26.1features ................................................................................................................48 26.2overview ...............................................................................................................48 27 crc ? cyclic redundancy che ck generator .............. .............. .......... 49
iv 8074b?avr?02/12 xmega b3 27.1features ................................................................................................................49 27.2overview ...............................................................................................................49 28 lcd - liquid crystal display controller ... ................ ................. .......... 50 28.1features ................................................................................................................50 28.2overview ...............................................................................................................50 29 adc ? 12-bit analog to digi tal converter ............... ................ ............. 51 29.1features ................................................................................................................51 29.2overview ...............................................................................................................51 30 ac ? analog comparator ... .............. ............... .............. .............. .......... 53 30.1features ................................................................................................................53 30.2overview ...............................................................................................................53 31 programming and debugging ..... ................ ................. .............. .......... 55 31.1features ................................................................................................................55 31.2overview ...............................................................................................................55 32 pinout and pin functions ................. ............... .............. .............. .......... 56 32.1alternate pin function description ........................................................................56 32.2alternate pin functions .........................................................................................58 33 peripheral module addr ess map ............... ................ ................. .......... 61 34 instruction set summary ... .............. ............... .............. .............. .......... 62 35 packaging information .......... .............. .............. .............. .............. ........ 66 35.164a ....................................................................................................................... .66 35.264m2 .....................................................................................................................6 7 36 electrical characteristics ... .............. ............... .............. .............. .......... 68 36.1absolute maximum ratings ...................................................................................68 36.2general operating ratings ....................................................................................68 36.3dc characteristics ................................................................................................70 36.4wake-up time from sleep modes ...........................................................................72 36.5i/o pin characteristics ...........................................................................................73 36.6liquid crystal display characteristics ....................................................................74 36.7adc characteristics ...............................................................................................74 36.8analog comparator characteristics .......................................................................77 36.9bandgap and internal 1.0v reference characteristics .........................................77 36.10brownout detection characteristics ....................................................................78
v 8074b?avr?02/12 xmega b3 36.11external reset characteristics ............................................................................78 36.12power-on reset characteristics ..........................................................................78 36.13flash and eeprom memory characterist ics .............. ................ ............. ..........79 36.14clock and oscillator characteristics .... ................................................................79 36.15spi characteristics ...............................................................................................85 36.16two-wire interface characteristics .....................................................................87 37 typical characteristics ....... .............. ............... .............. .............. .......... 89 37.1current consumption .............................................................................................89 37.2i/o pin characteristics ...........................................................................................94 37.3adc characteristics ............................................................................................100 37.4analog comparator characteristics .....................................................................106 37.5internal 1.0v reference characteristics ...............................................................109 37.6bod characteristics ............................................................................................110 37.7external reset characteristics ............................................................................112 37.8oscillator characteristics ....................... ..............................................................116 37.9pdi characteristics ..............................................................................................125 37.10lcd characteristics ..........................................................................................126 38 errata ........... ................ ................ ................. ................ .............. ........... 130 38.1atxmega64b3, atxmega128b3 .........................................................................130 39 datasheet revision history .. ................ ................. ................ ............. 131 39.18074b ?02/12 ......................................................................................................131 39.28074a ? 10/11 .....................................................................................................131 table of contents ............. ................ ................. ................ .............. ........... i
8074b?avr?02/12 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 16f, shin osaki kangyo bldg. 1-6-4 osaki shinagawa-ku tokyo 104-0032 japan tel : (+81)(3) 6417-0300 fax : (+81)(3) 6417-0370 ? 2012 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , qtouch ? , avr studio ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. windows ? and others are registered trademarks of microsoft corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life.

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